Signaling accommodation

ABSTRACT

A receiving unit may implement voltage compensation using a parameters table, an analog calibration component, and/or a digital calibration component. In certain implementation(s), an integrated circuit may include a voltage driver that modifies a supplied compensated voltage based on a feedback signal. The feedback signal may be produced responsive to a distributed voltage version of the compensated voltage, to a received data signal, and to a comparison involving an expected data value. In other implementation(s), a parameters table may be initialized by storing calibration values in entries in association with respective multiple identifications of multiple external points. In still other implementation(s), a particular calibration value of multiple calibration values may be ascertained, with the particular calibration value associated with a particular external point; the particular calibration value may be activated; and data from the particular external point may be received using the particular calibration value. Other implementations are also described.

CROSS-REFERENCE(S) TO RELATED APPLICATION(S)

[0001] This United States Nonprovisional Application for Letters Patentis a continuation-in-part of U.S. Nonprovisional Application for LettersPatent Ser. No. 10/076,666, filed on Feb. 14, 2002. U.S. NonprovisionalApplication for Letters Patent Ser. No. 10/076,666 is herebyincorporated by reference in its entirety herein.

TECHNICAL FIELD

[0002] This disclosure relates in general to the field of signalingaccommodation, and in particular, by way of example but not limitation,to making accommodations for different types of signals being receivedunder various conditions.

BACKGROUND

[0003] As complementary metal oxide semiconductor (CMOS) and othersemiconductor technologies shrink in size, there are correspondingimprovements in device capacity, bandwidth, and cost. Furthermore, asfrequencies of devices and buses increase, the performance ofelectronics may also increase proportionally. However, shrinking processtechnologies and increasing frequencies also present challenges, oftenrequiring designers to compensate for various undesirable side-effects.

[0004] As an example, as semiconductor processing technologies haveimproved, the interconnect traces that semiconductor devicemanufacturers use to interconnect components on integrated circuits havebecome much smaller in both width and depth. Because of this, suchtraces are often more resistive than in the past. Furthermore, smallersizes and thinner oxide layers often increase the current leakage oftransistor gates. These two factors combine to produce higher voltagedrops along device interconnect traces. Such voltage drops can poseproblems in many situations, including for example, reduced voltagemargins and decreased signal integrity.

[0005] The increased density and higher operational frequencies ofsemiconductor devices also increase the coupling of noise from adjacenttraces and device elements. Compounding these problems is the tendencyof many newer devices to utilize lower signal voltages. Voltage drop andnoise coupling become even more problematic in the face of such lowerabsolute and relative voltages. Furthermore, Ad real-world devices ingeneral suffer from manufacturing process imperfections and experiencenominal voltage and temperature variations during operation.

[0006] Various forms of differential signaling are often used to addressthe problems mentioned above. In one form of differential signaling,often referred to as “pseudo-differential” signaling, a common referencevoltage is distributed to multiple signal receivers. Signal voltages arethen specified relative to the common reference voltage. Such signalvoltages may be digital or analog in nature. Regardless, the multiplesignal receivers interpret respective data signal voltages by comparingeach of them to the common reference voltage to produce output signalvoltages.

[0007] To reduce the effects of voltage drops and noise coupling, both asignal (such as a data signal) and its associated reference voltage maybe given similar physical routings. Because of their similar routings,both the signal voltage and the reference voltage are subject to similardegrading influences (such as voltage drop and noise coupling), and thesignal voltage therefore maintains a generally fixed—or at leastproportional—relationship with the reference voltage.

[0008] Within a given integrated circuit, using similar physicalroutings for a signal and its associated reference voltage is effectiveto some degree, but it can be inadequate in devices where interconnectresistances are high and/or where there are large leakage currents. Atypical individual physical routing has a resistance that increases asits length increases. A voltage drop over such a physical routing may becalculated as the product of the resistance and any leakage currentproduced by devices connected by way of the routing. As an example, thetraces of a modern CMOS process might exhibit a resistance of 100 milliOhms per micron of trace length. Leakage currents might be on the orderof 200 nano Amps per square micron. Assuming a trace length of 1000microns and a trace width of 0.33 microns, a typical interconnectionscheme might produce a voltage drop of approximately 192 milli Voltsbetween a nominal reference voltage and the “actual” reference voltageas it is received by various components, including “pseudo-differential”signal receivers.

[0009] Such a drop in actual reference voltage can result insignificantly decreased margin or “headroom” between the actualreference voltage and ground. Also, as the reference voltage approachesground, there is a concomitant reduction in the range of voltages thatqualify as “low” in comparison to the reference voltage. Consequently,the circuitry exhibits increased sensitivity to noise. The problem isparticularly acute in high-speed devices where even the nominal or idealreference voltage value is relatively low. In devices such as these, anyfurther lowering of the nominal reference voltage threatens tosignificantly impair device operation. Furthermore, as semiconductorprocess technologies continue to shrink and to operate at ever higherfrequencies, and as operating voltages continue to decrease, these typesof interconnect-related voltage drops will become even more significant.

[0010] When two integrated circuit (IC) chips are engaged in acommunication, a signal may be transmitted from one chip and received atanother chip. The signal may be a signal voltage that is transmittedover a channel between a transmitting chip and a receiving chip. Inaddition to voltage changes (such as voltage drops) that result frominterconnect traces that are internal to a given IC chip that isreceiving a data signal (i.e., those voltage changes within a receivingchip), voltage changes can result from effects internal to atransmitting chip and from effects of a channel that interconnect thetransmitting and receiving chips. For example, channel DC resistanceinduces voltage errors in many current signaling systems. Because ofchannel DC resistance, a data signal can shift in voltage as ittraverses a signaling channel. Consequently, the farther apart two chipsare located on a given signaling channel, the greater the voltage swingreduction that is likely to occur because of increasing channel DCresistance that forms a voltage divider with termination resistance.

[0011] In short, data signaling voltages can be adversely affected byincreasing and/or differing resistances and currents, by increasingfrequencies, by noise corruption, etc. due to effects both internal toone or more chips and the data signaling channel therebetween. Takenindividually, any one of these factors can result in data signalingerrors. Collectively, these factors can severely impact the ability toproperly detect received data signaling—especially if data signalingvoltage changes and “actual” reference voltage changes occur inconverging directions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the Drawings, like numerals are used for like and/orcorresponding features, aspects, and components of the various FIGS.1-11C.

[0013]FIG. 1 illustrates signaling between exemplary electronic units.

[0014]FIG. 2 illustrates an exemplary computing system having componentsthat are capable of signaling.

[0015]FIG. 3A illustrates an exemplary memory system having memorymodules that are capable of signaling.

[0016]FIG. 3B illustrates exemplary data signaling graphs withaccompanying voltage swings and voltage margins.

[0017]FIG. 4A illustrates an exemplary scheme for providing acompensated voltage when receiving signals.

[0018]FIG. 4B illustrates an exemplary method in flowchart form forproviding a compensated voltage when receiving signals.

[0019]FIG. 5 illustrates multiple exemplary approaches to implementingthe exemplary scheme for providing a compensated voltage when receivingsignals.

[0020]FIG. 6 is a schematic view of an exemplary implementation of areference voltage driver such as may be used in the scheme of FIG. 4A etseq.

[0021]FIG. 7 is a schematic view of another exemplary implementation ofa reference voltage driver such as may be used in the scheme of FIG. 4Aet seq.

[0022]FIG. 8 is a schematic view of yet another exemplary implementationof a reference voltage driver such as may be used in the scheme of FIG.4A et seq.

[0023]FIG. 9A is a schematic view of an exemplary analog calibrationapproach for providing a compensated voltage when receiving signals.

[0024]FIG. 9B is a flowchart illustrating an exemplary method forproviding a compensated voltage using an analog calibration approach.

[0025]FIG. 10A is a block diagram view of an exemplary digitalcalibration approach for providing a compensated voltage when receivingsignals.

[0026]FIG. 10B is a flowchart illustrating an exemplary method forproviding a compensated voltage using a digital calibration approach.

[0027]FIG. 11A is a block diagram view of an exemplary parameters tableapproach for accommodating signaling.

[0028]FIG. 11B illustrates an exemplary parameters table.

[0029]FIG. 11C is a flowchart illustrating an exemplary method foraccommodating signaling using a parameters table approach.

DETAILED DESCRIPTION

[0030]FIG. 1 shows a system 100 that employs signaling between exemplaryelectronic units. A transmitting unit 105 sends a signal 110 to areceiving unit 115. The receiving unit 115 receives the signal 110 fromthe transmitting unit 105. The units 105 and 115 include components fortransmitting and/or receiving the signal 110, and each may additionallyinclude other components related to other functions. Although only asingle signal 110 is shown being transmitted from the transmitting unit105 to the receiving unit 115, in many cases there may be multiplesignals transmitted from the transmitting unit 105 to the receiving unit115, and the units shown may have multiple transmitters and receiversfor handling such multiple signals.. Additionally, one or more signalsmay be transmitted from the receiving unit 115 to the transmitting unit105, as indicated by the dashed arrow representing optional signal(s)120.

[0031] The transmitting unit 105 and the receiving unit 115 may be onthe same integrated circuit, may be on different integrated circuits(e.g., on a single printed circuit board (PCB) or different PCBs), maybe on separate components (e.g., separate cards, modules, etc. connectedby one or more buses, etc.), and so forth.

[0032] Although the signal(s) can be any general signal capable ofcommunicating information, the signals may be digital or analog signalsin the described implementation(s). If the signals are digital, forexample, they may relate to memory read/write data, control data,address data, and so forth. However, such digital signals may moregenerally represent binary data in any computing system.

[0033] The signal 110 is subject to signal degradations—such as voltagechanges—as it propagates between the transmitting unit 105 and thereceiving unit 115. In order to mitigate the effects of such signaldegradations, voltage compensation schemes and techniques (details ofwhich are described below) may be implemented. Implementation of part orall of the described voltage compensation schemes and techniquesfacilitate a more accurate reception of the signal 110 at the receivingunit 115. Such voltage compensation schemes and techniques may be atleast partially effective even when nominal or intended voltages havechanged due to factors that are internal to the receiving unit 115,internal to the transmitting unit 105, external to the two units 105 and115 (e.g., related to a channel therebetween), some combination thereof,and so forth.

[0034]FIG. 2 illustrates an exemplary computing system 200 havingsignaling components. Both the computing system 200 as a whole and theindividual components thereof may act as a receiving unit 115 (of FIG.1). For example, the components of the computing system 200 may receivesignals over the bus 205, and they may therefore constitute receivingunits 115. When a given component is also capable of sending signals, itmay constitute a sending unit 105 in a particular signal exchangebetween two units. The bus 205 may be wires, interconnects across a PCB,and so forth.

[0035] The exemplary computing system 200 includes one or moreprocessors 210, a video system 215 (e.g., a graphics card or similar),and other input/output 220 hardware. The exemplary components mayadditionally include a memory system 225 (e.g., a so-called primarymemory system), a secondary memory system 230, and other components 235.Each of these components potentially acts as a transmitting unit and/ora receiving unit with respect to one or more signals. Each illustratedcomponent might be implemented as a single device or as a combination ofdiscrete devices.

[0036]FIG. 3A illustrates an exemplary memory system 225 having memorymodules 310 and 315 that are capable of signaling. In the describedimplementation, a memory controller module 310 is capable ofcommunicating is with memory storage modules 315A and 315B over a bus305. The memory modules 310 and 315 may be discrete components such asICs, and they are able to communicate over the bus 305 using signaling.The bus 305 may interconnect the memory modules 310 and 315 using any ofmany possible bus architectures and protocols. For example, the memorymodules 310 and 315 may operate in a master-slave relationship, aslabeled parenthetically. In such a relationship, the master engages in abi-directional communication with any of multiple slaves, while each ofthe slaves communicates bi-directionally with the master. Consequently,any one or more of the memory modules 310 and 315 may comprise at leasta receiving unit, and optionally a transmitting unit.

[0037] More specifically, in the exemplary implementation of FIG. 3A, amemory controller module 310 controls (e.g., controls reads from andwrites to) one or more memory storage modules 315. Although only twosuch memory storage modules 315A and 315B are illustrated, three, four,or more memory storage modules 315 as indicated by the ellipses mayalternatively be controlled by one or more memory controllers 310. Thememory modules 310 and 315 form a memory system constructed and/oroperating in accordance with any one or more of many different types ofmemory. These different types of memory include, but are not limited to,dynamic random access memory (DRAM), extended data out (EDO) DRAM,static random access memory (SRAM), synchronous DRAM (SDRAM), doubledata rate (DDR) SDRAM, Rambus® DRAM, and so forth.

[0038] Thus, the memory storage modules 315A and 315B each includemultiple memory storage cells. (The memory controller 310 may alsoinclude storage cells, especially those used for buffering, such ascaching, transfer latching, and so forth.) The memory controller 310 andthe memory storage modules 315 may each include various control circuitsto facilitate writing to and reading from the multiple memory storagecells.

[0039] Each of the memory storage modules 315 includes and/orcorresponds to an identification (ID) 325. The ID 325 may be any form ofidentification that enables the memory controller 310 to locate and/orcommunicate with a particular memory storage module 315. For example,the ID 325 may be a code, a logical address, a physical place on the bus305, an alpha and/or numeric designation, and so forth. If thedesignation is alphanumeric, the ID 325 may be unique on a memory system225 level, on a computing system 200 level, on a general level (e.g.,with respect to all such memory storage modules 315), and so forth. Thememory controller 310 may also include an ID 325 (not explicitly shown).

[0040] To facilitate communication with the multiple memory storagemodules 315, especially if they differ from one another by type, thememory controller module 310 may include a parameters table 320. Theparameters table 320, or more generally a parameters data structure,includes multiple entries, with each entry having an ID 325 andassociated attribute(s). The number of entries may correspond to thenumber of memory storage modules 315 with which the memory controller310 may wish to communicate. Attributes related to a particular memorystorage module 315 are associated with the ID 325 of that particularmemory storage module 315 in and entry of the parameters table 320.Attributes may be related to a particular memory storage module 315because of its general or specific memory type or because of anindividual component analysis (e.g., as determined by analysis during acalibration period). Utilizing the attributes in the parameters table320 (e.g., during an operational period) may enable and/or at leastpartially optimize communications with the memory storage modules 315.

[0041] Many of these memory modules 310 and 315 may also includedifferential and/or pseudo-differential receivers for internal and/orchip-to-chip data communications. Such memory modules, and thedifferential and/or pseudo-differential receivers, may therefore rely tovarying degrees on various types of voltages, including referencevoltages. In fact, correct and accurate operation thereof may depend onmaintaining these voltages within very close tolerances.

[0042]FIG. 3B illustrates exemplary data signaling graphs withaccompanying voltage swings and voltage margins. Three data signalinggraphs 350A, 350B, and 350C plot time [T] versus voltage [V] for threesignals A, B, and C whose voltages are meaningful in comparison to anominal reference voltage (V_(NOM)). In the graph 350A, the signal A hasarrived at a receiving unit without any voltage attenuation or offset.Consequently, the common mode voltage (V_(CM)) of the signal A is equalto the nominal reference voltage (V_(NOM)). The common mode voltage maybe considered as an average voltage of the incoming signal. For example,the common mode voltage point for a fifty percent (50%) duty cyclesignal is in the center of the voltage swing. Because the nominalreference voltage is equal to the common mode voltage in the graph 350A,the full voltage swing (and hence the full timing margin) is availablefor correctly detecting/interpreting a received data signal.

[0043] Typically, however, signals do undergo voltage attenuation and/oroffset prior to and while arriving at a receiving unit and/or a signalreceiver. For example, in the graph 350B, the signal B has arrived at areceiving unit with no voltage attenuation but with a noticeable (anddetectable) voltage offset. Consequently, the common mode voltage(V_(CM)) of the signal B does not equal the nominal reference voltage(V_(NOM)). As a result, the voltage margin on the lower side (thedifference between V_(NOM) and the lower extreme of signal B) isreduced, which can interfere with correct detection/interpretation of areceived data signal.

[0044] The voltage margin that is otherwise reduced may be increasedusing a compensated voltage scheme when receiving the signaling. In thegraph 350C, the signal C has also arrived at a receiving unit with novoltage attenuation but with noticeable and detectable voltage offset.Consequently, the common mode voltage (V_(CM)) of the signal C againdoes not equal the nominal reference voltage (V_(NOM)). However, signalreceiver(s) that receive the signal C and a reference voltage areprovided a compensated reference voltage (V_(COMP)*). The compensatedreference voltage is set so that the actual reference voltage receivedat the signal receiver is approximately equal to the common mode voltageof the signal C. (The actual reference voltage received at the signalreceiver is designated “V_(DIS)” in the graph 350C to reflect the“distributed voltage” terminology used below in FIG. 4A et seq.) Settingthe actual reference voltage received at the signal receiver to beapproximately equal to the common mode voltage of the signal has theeffect of increasing the voltage swing (and the related timing margin)available for correct data signal detection and interpretation.

[0045] While not so limited, the schemes and techniques described hereinare particularly useful for voltage compensation with ICs, especiallythose connected via high speed buses/channels. With ICs that areconnected via high speed channels, the shrinking geometries of the ICshave resulted in interconnect traces having increasingly higherimpedances, and the accelerating signaling frequencies of the channelshave resulted in increasingly shorter timing margins. For example, asalluded to above with reference to FIGS. 1-3A, the subject matterdescribed herein may be used to compensate voltages distributed orotherwise propagated between or among discrete components of PCBs, aswell as other circuits.

[0046] The Applicants have found that these schemes and techniques maybe particularly beneficial in various types of IC memory and PCB memorycircuits, such as dynamic memory devices and boards, as described abovewith reference to FIG. 3A. Many high-speed memory technologies utilizedifferential and/or pseudo-differential signaling techniques, and it isparticularly beneficial in these types of circuits to keep distributedvoltages and signaling voltages within close tolerances.

[0047]FIG. 4A illustrates an exemplary scheme 400 for providing acompensated voltage when receiving signals. The elements of the scheme400 may be part of a memory module 310/315 (of FIG. 3), a component210-235 (of FIG. 2), or more generally a receiving unit 115 (of FIG. 1).Thus, the scheme 400 may be implemented as an IC using, for example, asemiconductor processing technology, such as CMOS and bipolar processingtechnologies, as well as by other present and future circuittechnologies. Also, the scheme 400 may alternatively be implementedusing a printed circuit board (utilizing for example PCB fabricationtechnology) and/or using discrete devices.

[0048] Generally, in the described implementation, the scheme 400includes a reference voltage driver 410, one or more components 405, anda feedback unit 420. These elements form a feedback system thatcompensates for at least some of the voltage changes that can occur to asignal. The reference voltage driver 410 supplies a compensatedreference voltage V_(comp) to the components 405. At the components 405,the supplied voltage comprises a distributed reference voltage V_(dis).The components also receive data signals D to be compared to thedistributed reference voltage V_(dis) in pseudo-differential fashion. Adesirable voltage margin for determining the data in the data signals Dis attained at the components 405 when the common mode voltage of thedata signals D at the components is equal to the distributed referencevoltage V_(dis). Unfortunately, they are frequently not equal absentintervention. The feedback unit 420, however, remedies or amelioratesthis inequality by adjusting, at least indirectly, the distributedreference voltage V_(dis) so that it is approximately equal to thecommon mode voltage of the data signals D at the components 405. Thefeedback unit 420 is typically active during calibration/initializationphases and inactive during operational phases.

[0049] More specifically, the one or more components 405 operate withreference to distributed reference voltages. In the describedimplementation, the components 405 comprise means for evaluating aplurality of data signals relative to a distributed reference voltage.More specifically, such means comprise a plurality of signal receivers,designated by reference numerals 405A, 405B, through 405N. The signalreceivers 405 are configured to evaluate corresponding signals D_(a),D_(b), through D_(n) relative to the distributed reference voltageV_(dis). Although three signals and three signal receivers are shown inFIG. 4A, the principles described herein may be implemented with anynumber of signals and signal receivers, as indicated by the ellipses andthe “N/n” suffixes.

[0050] Although the signal receivers shown in FIG. 4A can be ofdifferent types, the described implementation utilizes differential datareceivers, each of which compares two input voltages and produces abinary output signal as a function of which of the voltages is greater.The binary output signals are designated in FIG. 4A as O_(a), O_(b),through O_(n), while the respective received data signals that are beingcompared are designated as D_(a), D_(b), through D_(n). In theconfiguration shown, a first of the two inputs of a particular signalreceiver 405 receives distributed reference voltage V_(dis). The secondof the two inputs receives a data signal D, which is specified andevaluated relative to V_(dis) to represent a binary value. For example,a binary “1” might represent a data signal D that is greater thanV_(dis), while a binary “0” might represent a data signal D that is lessthan V_(dis). Alternatively, a different (e.g., an opposite) logicassignment may be employed.

[0051] The scheme 400 further comprises driver means having a variablevoltage gain for producing a compensated reference voltage. Such drivermeans in the described embodiment comprises a reference voltage driver410 that produces a compensated reference voltage V_(comp). Routingmeans are provided for routing the compensated reference voltageV_(comp) (e.g., on an IC) to form the distributed reference voltageV_(dis), at the signal receivers 405. Specifically, the compensatedreference voltage V_(comp) is routed on the IC through signal lines(e.g., traces) to the individual signal receivers 405. At the signalreceivers 405, the voltage comprises the distributed voltage V_(dis).

[0052] Compensated reference voltage V_(comp) is subject to signaldegradations such as noise coupling and voltage changes over the lengthsof the traces. The degraded reference voltage is what is received bycomponents 405A through 405N; therefore, V_(dis) is a degraded orvoltage-changed version of V_(comp). Depending on the direction ofcurrent leakage, V_(dis) might be either higher or lower than V_(comp).In a circuit where the input stages of components 405A through 405N sinkcurrent, the voltage degradation of V_(dis) will normally correspond toa voltage drop relative to V_(comp). In circuits where the input stagesof components 405A through 405N source current, the voltage degradationof V_(dis) will normally correspond to a voltage increase relative toV_(comp).

[0053] More specifically, the distribution traces have finiteresistances or impedances along their lengths that contribute to thedegradation or voltage change of distributed reference voltage V_(dis)with respect to V_(comp). Such resistances are represented in FIG. 4A byfinite resistor elements R_(r), although it should be recognized thatthe resistances are distributed along the lengths of the traces ratherthan being discrete elements. Also, each of the resistance values thatare designated by R_(r) ordinarily differ from each other, at leastslightly. Furthermore, signal receivers 405 have input characteristicsthat contribute to the degradation of distributed reference voltageV_(dis). Such input characteristics typically include finite inputimpedances and/or leakage currents.

[0054] Specifically, the signal receivers 405 have first input leakagecurrents that are represented in FIG. 4A by the symbol I_(r). It shouldbe noted that although the leakage currents I_(r) typically result frominput characteristics of the signal receivers 405 such as CMOS gateleakage, they could also be due to other factors. For example, somecircuits might utilize an input capacitance to reduce high-frequencynoise or to perform some other function. Such an input capacitance canbe an additional source of leakage current. Furthermore, leakagecurrents I_(r) might be either positive or negative, depending onwhether the signal receiver input is a current source or a current sink.In a circuit implemented with bipolar transistor technology, forexample, a receiver input might comprise the base of a bipolartransistor. If the transistor is an NPN transistor, there will normallybe a positive base current into the receiver input. If the transistor isa PNP transistor, on the other hand, the base will typically source anegative base current.

[0055] As discussed above in the “Background” section, trace resistancesand leakage currents can be a significant cause of voltage signaldegradation, including reference voltage signal degradation.Specifically, these factors can cause a voltage change in distributedreference voltage V_(dis) relative to compensated reference voltageV_(comp) (either an increase or a decrease, depending on thedirection(s) of the leakage currents I_(r)). This voltage change is atleast partially a function of the lengths of the traces and the inputcharacteristics of the signal receivers 405.

[0056] Compensated reference voltage V_(comp) may be distributed in astar, Kelvin, length-matched, or impedance-matched configuration toapproximately equalize signal degradations in distributed referencevoltage V_(dis) as it is received by the various signal receivers. Inaddition, data signals D are typically routed in a fashion similar tothat of the distributed reference voltage V_(dis) so that the datasignals D are subject to approximately the same degradations asdistributed reference voltage V_(dis). A signal, including data signals,may be considered to start as an original version of the signal. Afterdegradations thereto, the degraded signal may be considered a degradedversion of the signal. Furthermore, after a signal has been offset orhad a common mode adjustment, the altered signal may be considered asyet another version of the signal. Hence, as a signal experiencesvarious changes, different versions of the signal may be produced.

[0057] Generally, the various signal paths to the inputs of the signalreceivers 405 are designed to have matching impedances, to result insimilar voltage degradations over the lengths of the signal paths. Insituations where the respective conductors or traces that convey V_(dis)to the various signal receivers have approximately the same physicaland/or electrical characteristics (e.g., similar conductive metal,width, and thickness), the conductors are simply length-matched toachieve such impedance matching. In many cases, the signal paths orconductors may be considered to be matched if their impedances fallwithin approximately 10% of each other, although various circuits mightrequire more or less matching precision, depending on the nature of thecircuits and process technologies utilized. In some applications, on theother hand, it may be desirable to match impedances to within 1%.

[0058] Thus, due to matching impedances and current flows across themultiple traces, each distributed voltage V_(dis) is approximately equalto the other distributed voltages V_(dis). Because of the variousdegrading factors, each distributed voltage V_(dis) is the “actual”reference voltage provided to the signal receivers, and it may beconsidered a version of the compensated reference voltage V_(comp) asmodified by interconnect trace and other effects between the point ofgeneration of the compensated reference voltage V_(comp) and the pointof supply to the signal receivers.

[0059] It is therefore this distributed voltage V_(dis) that is setequal to a common mode voltage of a received signal D to improve thevoltage margin. In other words, by setting a modified version of thecompensated reference voltage V_(comp) (i.e., the distributed voltageV_(dis) in this context) equal or approximately equal to the common modevoltage of the received signal, the voltage swing (and the relatedtiming margin) that is available for correct data signal detection andinterpretation may be increased. To achieve this, the compensatedreference voltage V_(comp) is directly adjusted, and the distributedreference voltage V_(dis) is consequentially indirectly adjusted, toaccount for the variations in the common mode voltages of the receivedsignals.

[0060] These variations in the common mode voltage of the receivedsignals D are due to a number of factors that are frequently not easy topredict and/or to remove through passive design in an IC chip or an ICsystem. For example, as also described above, the common mode voltage ofa received signal may differ from that of the “best known” ordesigned-for signal receiver input voltage due to any one or more of anumber of factors, including the following: the duty cycle of thesignal, an asymmetry of the output transmitter (e.g., of a transmittingunit), a difference in output waveform edge rate, channel loading, andso forth.

[0061] The above factors can cause a loss of system margin due tounbalanced signaling. In the implementation illustrated in FIG. 4A,these and other factors that affect received signaling are representedby the resistor elements R_(S) and the second input leakage currentelements I_(S). It should be recognized that the “resistances” mayactually be more-electrically-complex impedances and that they aredistributed from the transmitting unit, along an interconnectingchannel, and to/into the receiving unit, rather than being discreteelements. Also, each of the resistance values that are designated byR_(S) ordinarily differ from each other, at least slightly.

[0062] Furthermore, the signal receivers 405 have input characteristicsthat also contribute to the degradation of the received signal D. Suchinput characteristics typically include finite input impedances and/orleakage currents (e.g., that create or contribute to the second inputleakage currents I_(S)) that are also represented by the resistors R_(S)and the second input leakage currents I_(S). Again, it should be notedthat although the leakage currents I_(S) typically result from inputcharacteristics of the signal receivers 405 such as CMOS gate leakage,they could also be due to other factors, including those external to thereceiving unit. In short, the factors affecting the integrity of thereceived signals D, as represented by the resistors R_(S) and the secondinput leakage currents I_(S), may actually be fully or partially createdexternal to the receiving unit. It is these factors affecting theintegrity of the received signals D that lead to variances in the commonmode voltage of the received signals D.

[0063] In FIGS. 4A et seq., compensation for these variances of thecommon mode voltage of the received signals D is accomplished throughvoltage adjustment. In the described implementation, the voltage that isultimately adjusted to achieve the compensation is the distributedreference voltage V_(dis) at the signal receivers 405. The distributedreference voltage V_(dis) is adjusted so that it approximately equalsthe common mode voltage of the received signals D at the signalreceivers 405. The distributed reference voltage V_(dis) is indirectlyadjusted as a result of the direct adjustment of the compensatedreference voltage V_(comp) by the reference voltage driver 410. Thereference voltage driver 410 compensates the compensated referencevoltage V_(comp) responsive to a feedback signal F*, which is producedby the feedback unit 420 during calibration/initialization periods. Thefeedback unit 420 receives as input the distributed reference voltageV_(dis) and the data signal D_(n), which are used to produce as outputthe feedback signal F*.

[0064] There is therefore a feedback loop that compensates for“non-ideal” common mode voltage values of the received signals D at thesignal receivers 405 by setting the distributed reference voltageV_(dis) approximately equal to the common mode voltage value of thereceived signal D_(n). Describing this feedback loop in the otherdirection, the feedback unit 420 receives as input the distributedreference voltage V_(dis) and the received data signal D_(n). Thefeedback unit 420 produces the feedback signal F* responsive to thesetwo inputs and a comparison involving an expected data value, examplesof which are provided in the following paragraph. Using the feedbacksignal F*, the reference voltage driver 410 directly adjusts/modifiesthe compensated voltage V_(comp) and therefore indirectly adjusts thedistributed voltage V_(dis). The distributed voltage V_(dis) is adjustedso as to approximate the common mode voltage V_(cm) (not explicitlyshown in FIG. 4A) of the received data signal D_(n). The common modevoltage V_(cm) of the received data signal D_(n) is therefore determinedusing the feedback unit 420 and the reference voltage driver 410.

[0065] In one implementation, the expected data value, used as part ofan internal comparison within the feedback unit 420 to produce thefeedback signal F*, comprises a predetermined test value. Moregenerally, the expected data value might be based on operationalmeasurements; on a data value that is provided (e.g., from atransmitting unit) to the receiving unit, including to the feedback unit420 or other control circuitry; on a data value that has been provided(e.g., to a transmitting unit) from the receiving unit, including fromthe feedback unit 420 or other control circuitry; and so forth. Morespecifically, but by way of example only, a receiving unit employing thescheme 400 of FIG. 4A may send a data value to a transmitting unit andthen request that the transmitting unit return the data value to thereceiving unit by transmitting it back as a data signal. The receiveddata signal, or a derivative thereof, may then be compared to anexpected data value, which may be derived from the data value sent tothe transmitting unit. Particular exemplary expected data values and/oraspects thereof are described herein with reference to FIGS. 9A, 9B,10A, and 10B.

[0066] In the described implementation, the feedback unit 420 includesat least one signal receiver 405N and one or more calibration components415. The signal receiver 405N has first and second inputs and oneoutput. The first input receives the distributed voltage V_(dis), andthe output provides output signal O_(n). The signal received by thesecond input of the signal receiver 405N depends on which of twoembodiments the feedback unit 420 is operating under. The first andsecond embodiments are determined based on where and how the calibrationcomponent 415 is located and operating. The two options are reflecteddiagrammatically by the left and right dashed extensions of thecalibration component 415 in FIG. 4A.

[0067] In the first embodiment of the implementation of FIG. 4A, thecalibration component 415 is located prior to the second input of thesignal receiver 405N. The calibration component 415 in this firstembodiment receives as input the received signal D_(n) and provides asoutput the second input to the signal receiver 405N. The output O_(n) ofthe signal receiver 405N is the feedback signal F. In this firstembodiment, the feedback signal F, without further modification, alsoforms the feedback signal F*, which is received by the reference voltagedriver 410.

[0068] In the second embodiment of the implementation of FIG. 4A, thecalibration component 415 is located after the output O_(n) of thesignal receiver 405N. The signal receiver 405N in this second embodimentreceives as its second input the received signal D_(n) and produces asits output O_(n) the feedback signal F. The calibration component 415receives as input the feedback signal F and is provides as output thefeedback signal F*, which is received by the reference voltage driver410. Additional details regarding the first and second embodiments ofthe calibration component 415 are described below with reference to FIG.5 et seq.

[0069] In the described implementations, the “feedback” signal receiver405N of the feedback unit 420 comprises one signal receiver of the(usually) multiple signal receivers 405. In other words, a “standard”signal receiver 405 is used as the feedback signal receiver 405N, withthe feedback signal receiver 405N having the same or similar electricalcharacteristics as the other signal receivers 405. When a “standard”signal receiver 405 is shared for the feedback unit 420, the inputthereto may have the calibration component 415 isolated to match theother “standard” signal receivers 405 in terms of loading during theinitialization period(s).

[0070] Other implementations, however, might utilize a “special” ordedicated additional signal receiver as a feedback component duringinitialization period(s). To accomplish this, the data signal D_(n) maybe diverted, re-routed, and/or otherwise shunted to an input of such a“special” dedicated additional signal receiver during initialization,along with the distributed voltage V_(dis) to another input thereof.During normal operational periods, the “special” dedicated additionalsignal receiver can be dormant. Alternatively, calibration may occurconstantly using a dedicated signal receiver that constantly receives acalibration signal from the transmitting unit under consideration on adedicated connection (e.g., line or bus) between that transmitting unitand the signal receiver of the receiving unit.

[0071]FIG. 4B is a flowchart illustrating an exemplary method forproviding a compensated voltage when receiving signals. The flowchart450 includes actions 455-475 that are directed to aninitialization/calibration phase where compensation values and/or levelsare being initially determined. These actions 455-475 may be performedin an order other than that illustrated and/or fully or partially(substantially) simultaneously. Actions of the flowchart 450 may beperformed in a receiving unit, whether the receiving unit be a discretepart, an IC, a component on a PCB, a memory system, a computer, and soforth. Furthermore, the actions 455-475 are described below withreference to the hardware already described in FIG. 4A, but they can beperformed by other hardware.

[0072] An action 455 comprises sending an expected or predetermined datavalue to an external point. This data value can be sent from a receivingunit (having transmitting functionality, too) that includes the scheme400. The external point can be a transmitting unit (having receivingfunctionality, too). Both of the receiving unit and the transmittingunit can be a discrete part, an IC, a component on a PCB, a memorysystem, a computer, and so forth.

[0073] An action 460 comprises supplying a voltage. The voltage cancomprise the distributed reference voltage V_(dis), being supplied tothe receiving unit 405N. (The voltage can “initially” be supplied by thereference voltage driver 410 as the compensated reference voltageV_(comp).) An action 465 comprises receiving a data signal from theexternal point. The data signal may be sent from the transmitting unitbased on the predetermined data value that was previously sent thereto,and it may be received at the receiving unit as the signal D_(n). Anaction 470 comprises producing a feedback signal responsive to the datasignal, the supplied voltage, and an expected data value. The expecteddata value may be the predetermined data value that was previously sentto the transmitting unit, a derivative thereof, an attribute of a signalcarrying the predetermined data value, and so forth. Thus, the expecteddata value can comprise, for example, a voltage level, a binary value,and so forth. The feedback signal may be the feedback signal F* that isoutput from the feedback unit 420.

[0074] An action 475 comprises modifying the voltage being supplied inthe action 460 based on the feedback signal. In the describedimplementation, the reference voltage driver 410 receives the feedbacksignal F* and modifies the voltage output therefrom (the compensatedreference voltage V_(comp)), which is a version of the distributedreference voltage V_(dis). An arrow 480 leads from the action 475 backaround to the action 455 to indicate that all or some of the actions455-475 may be repeated during an initialization period, until thesupplied voltage reaches a satisfactory level. The supplied voltage,V_(dis), may be considered to have reached a satisfactory level when itbecomes approximately equal to the common mode voltage of the receivedsignal D_(n), as is described further below. As an example of thefeedback cycle represented by the arrow 480, actions 460-475 may berepeated after action 455 is performed once (e.g., optionally withrepeated instructions from the receiving unit to the transmitting unitto send the data signal).

[0075]FIG. 5 illustrates multiple exemplary approaches to implementingthe exemplary scheme 500 for providing a compensated voltage whenreceiving signals. The implementations shown in FIG. 5 include an analogcalibration component 505, a digital calibration component 510, and/orthe parameters table 320 (also illustrated in FIG. 3A). Each may be usedindividually or in conjunction with one or more of the others. Forexample, either the analog calibration component 505 or the digitalcalibration component 510 may be utilized in conjunction with theparameters table 320. Although the analog calibration component 505 andthe digital calibration component 510 may be utilized together forconfirmation or other synergistic purposes, it is more likely that onlyone or the other is implemented in any single receiving unit. In otherwords, it is more likely that only the analog calibration component 505or the digital calibration component 510 (with or without a parameterstable 320) is implemented within any given feedback unit 420.

[0076] It should be understood that the feedback unit 420 is activeduring initialization/calibration to determine calibration values and/orlevels. During operational periods, however, the feedback unit 420 isinactive. Thus, if the signal receiver 405N is shared for normaloperational signal reception, the received signal D_(n) is passedunchanged to the second input of the signal receiver 405N during suchoperational periods. The parameters table 320, on the other hand, can beactive during both calibration periods and operational periods. Duringcalibration the parameters table 320 receives determined calibrationvalues, and during normal operation the parameters table 320 providessuch calibration values for use in receiving signaling.

[0077] As is described above with reference to FIG. 3A, the parameterstable 320 includes multiple entries, with each entry including an ID andassociated attribute(s) for each transmitting unit from which datasignals are to be received. Utilizing one or more of the attributes in areceiving unit facilitates the correct interpretation of informationthat is received in data signals from transmitting units. When a signalis to be received or is being received from a particular transmittingunit having a particular ID, the entry in the parameters table 320 thatincludes that particular ID is accessed and at least one associatedattribute is extracted therefrom. The ID serves to identify a source (ordestination) of a signal, as is described above with reference to FIG.3A. The associated attribute may be a compensation value, and it mayindicate a level at which the voltage driver 410 should drive thecompensated voltage V_(comp) to achieve a given distributed voltageV_(dis). The given distributed voltage V_(dis), from previouscalibration efforts, is known to approximately equal the common modevoltage of data signals D from the identified signal source.

[0078] More generally, a compensation value is a register value oranother value that is capable of storing information that may set ormodify a voltage (or other changeable attribute such as timing). In animplementation of the scheme 500 in FIG. 5, each compensation value isused by the reference voltage driver 410 to set/modify the compensatedvoltage V_(comp). A particular compensation value is selected andactivated for utilization by the reference voltage driver 410 wheneverthe receiving unit employing the scheme 500 is to be receiving signalingfrom a particular transmitting unit having the ID that is associatedwith that particular compensation value in an entry of the parameterstable 320. Additional exemplary implementations for the parameters table320 are described below with reference to FIGS. 11A, 11B, and 11C. Inthe scheme 500, compensation values for the parameters table 320 aredetermined using the analog calibration component 505 or the digitalcalibration component 510, which are described below.

[0079] As is described above with reference to FIG. 4A, the calibrationcomponent 415 may be located either before an input of the signalreceiver 405N in a first embodiment or after the output of the signalreceiver 405N in a second embodiment. In the implementations shown inFIG. 5, these first and second embodiments of the calibration component415 are illustrated as the analog calibration component 505 and thedigital calibration component 510, respectively. Hence, when thecalibration is operating under an analog approach, the calibration iseffectuated using the analog calibration component 505. When thecalibration is operating under a digital approach, the calibration iseffectuated using the digital calibration component 515. In other words,usually only the analog calibration component 505 or the digitalcalibration component 510 will be implemented within a given embodimentof feedback unit 420.

[0080] When determining a compensation value using the analogcalibration component 505 and no digital calibration component 510, thefeedback signal F* is identical to and unchanged from the feedbacksignal F (excepting effects caused by trace impedance, etc.). In thisembodiment, the feedback unit 420 is configured so that it produces afeedback signal F/F* that is positive or logically true when thedistributed voltage V_(dis) is less than the common mode voltage V_(cm)(of a received data signal D_(n)) and negative or logically false whenthe distributed voltage V_(dis) is greater than the common mode voltageV_(cm). The common mode voltage V_(cm) of the received data signal D_(n)is determined using analog elements of the analog calibration component505 and provided as the second input to the signal receiver 405N, as isdescribed in greater detail below with reference to FIGS. 9A and 9B.

[0081] The signal receiver 405N compares the distributed voltage V_(dis)to the common mode voltage V_(cm) of the received signal D_(n) toproduce a result from which it may be determined whether an expectedvalue has been properly received with the received data signal D_(n).The result from the signal receiver 405N is the output O_(n), which isthe feedback signal F/F* in the analog calibration embodiment. Thereference voltage driver 410 is configured to respond to the feedbacksignal F/F* by increasing the compensated voltage V_(comp) when thefeedback signal F/F* is true and decreasing the compensated voltageV_(comp) when the feedback signal F/F* is false. The result is that thecompensated voltage V_(comp) is increased when V_(dis) <V_(cm) anddecreased when V_(dis) >V_(cm). This ensures that the distributedvoltage V_(dis) becomes (or remains) approximately equal to the commonmode voltage V_(cm). Exemplary manner(s) for determining whether acomparison involves an expected value and for controlling the referencevoltage driver 410 accordingly are described below with reference alsoto FIGS. 9A and 9B.

[0082] In an alternative implementation, the feedback unit 420 isconfigured so that it produces a feedback signal F/F* that is negativeor logically false when the distributed voltage V_(dis) is less than thecommon mode voltage V_(cm) and positive or logically true when thedistributed voltage V_(dis) is greater than the common mode voltageV_(cm); and the reference voltage driver 410 is configured to respond tothe feedback signal F/F* by increasing the compensated voltage V_(comp)when the feedback signal F/F* is false and by decreasing the compensatedvoltage V_(comp) when the feedback signal F/F* is true. Again, positivelogic, negative logic, or some combination thereof may be selected andimplemented for the described schemes and techniques.

[0083] In the second embodiment of the calibration component 415, thecompensation value is determined using the digital calibration component510. With no analog calibration component 505, the received data signalD_(n) is fed directly into the signal receiver 405N without modificationby any calibration component 415. Also, the feedback signal F isanalyzed and possibly changed by the digital calibration component 510to produce the feedback signal F*. When employing a digital calibrationcomponent 510, the feedback unit 420 is configured to determine high andlow compensated voltage V_(comp) failure points in conjunction with thereference voltage driver 410. The mid-point between these high and lowcompensated voltage V_(comp) failure points may be considered thedesired compensated voltage V_(comp). This mid-point compensated voltageV_(comp) is desired because a distributed version thereof, thedistributed voltage V_(dis), is approximately equal to the common modevoltage V_(cm) of the received data signal D_(n). Thus, using thismid-point compensated voltage V_(comp) improves the likelihood ofattaining a voltage swing (and hence a corresponding timing margin) atwhich the receiving unit (and optionally the transmitting unit) havebeen designed to operate, especially at the signal receiver(s) 405.

[0084] The reference voltage driver 410 is configured to respond to thefeedback signal F* by increasing the compensated voltage V_(comp) whenthe feedback signal F* is positive or logically true and decreasing thecompensated voltage V_(comp) when the feedback signal F* is negative orlogically false. For determining a high compensated voltage V_(comp),the digital calibration component 510 of the feedback unit 420 istherefore configured to maintain the feedback signal F* as positive aslong as there is no receiving failure. Consequently, the feedback signalF* is produced as positive or logically true when a comparison (e.g., atthe signal receiver 405N) of the distributed voltage V_(dis) to thereceived data signal D_(n) provides an expected result. For determininga low compensated voltage V_(comp), the digital calibration component510 of the feedback unit 420 is therefore configured to maintain thefeedback signal F* as negative as long as there is no receiving failure.Consequently, the feedback signal F* is produced as negative orlogically false when a comparison (e.g., at the signal receiver 405N) ofthe distributed voltage V_(dis) to the received data signal D_(n)provides an expected result.

[0085] The digital calibration component 510 determines whether anexpected value results from the comparison by knowing what the (e.g.,binary) value(s) of the received data signal D_(n) “should be”. Thevalue(s) of the received data signal D_(n) may be a single (e.g.,repeated) binary value or a string of binary values (e.g., of apredetermined length such as eight (8) bits). Consequently, while thedigital calibration component 510 determines that the received datasignal D_(n) continues to provide the expected binary value, itcontinues to maintain the feedback signal F* at its current logicalvalue. When, on the other hand, such a comparison of the distributedvoltage V_(dis) to the received data signal D_(n) does not provide theexpected result, the digital calibration component 510 considers this areceiving failure and notes the compensated voltage V_(comp) as anextreme, whether it be a high or low extreme. Exemplary manner(s) fordetermining whether a result is expected, for noting the compensatedvoltage V_(comp) extremes, and for controlling the reference voltagedriver 410 accordingly are described below with reference to FIGS. 10Aand 10B.

[0086] In an alternative implementation, the reference voltage driver410 is configured to respond to the feedback signal F* by decreasing thecompensated voltage V_(comp) when the feedback signal F* is positive orlogically true and increasing the compensated voltage V_(comp) when thefeedback signal F* is negative or logically false. For determining ahigh compensated voltage V_(comp), the digital calibration component 510of the feedback unit 420 is therefore configured to maintain thefeedback signal F* as negative as long as there is no receiving failure.Correspondingly, for determining a low compensated voltage V_(comp), thedigital calibration component 510 of the feedback unit 420 is thereforeconfigured to maintain the feedback signal F* as positive as long asthere is no receiving failure. Again, positive logic, negative logic, orsome combination thereof may be selected and implemented for thedescribed schemes and techniques.

[0087]FIG. 6 is a schematic view of an exemplary implementation of areference voltage driver 410 such as may be used in the scheme of FIG.4A et seq. In this implementation, the voltage driver 410 comprises anincrement/decrement component or up/down counter 630 and a variable gainamplifier 605. Generally, up/down counter 630 is configured to incrementand decrement a digital value 615 depending on the relationship of thedistributed reference voltage V_(dis) and the data signal D_(n) (or aderivative thereof such as the common mode voltage of the data signalD_(n)), as indicated by feedback signals F and F*.

[0088] Specifically, counter 630 increments value 615 whenV_(dis)<V_(cm) and decreases value 615 when V_(dis)>V_(cm), in an analogcalibration approach for example. Even more specifically, up/downcounter 630 has an up/down or +/−input 620 that receives feedback signalF*. When feedback signal F* is logically true, the counter periodicallyincrements digital output value 615. When feedback signal F* islogically false, the counter periodically decrements digital outputvalue 615. The output value 615 in this implementation may comprise aplurality of individual bit lines.

[0089] The counter 630 functions as a means of controlling the voltagegain of the voltage driver 410. The output value 615 is supplied to avariable gain amplifier 605, which has a variable gain that iscontrolled or established by the output value 615: higher values causethe amplifier 605 to have a higher gain, while lower values cause theamplifier 605 to have a lower gain. Thus, the gain of amplifier 605increases when V_(dis)<V_(cm) and decreases when V_(dis)>V_(cm), in ananalog calibration approach for example. An explanation for the valuesof F* in a digital calibration approach are described below.

[0090] In the illustrated implementation, the variable gain amplifier605 comprises an op-amp 610 that is capable of sinking or sourcingcurrent to provide positive or negative amplification of a nominalreference voltage V_(nom). Op-amp 610 is biased by resistors R_(g),R_(h), and R_(v1). A first input of op-amp 610 receives V_(nom) throughR_(g). A second input of amplifier 610 is connected to ground throughR_(h). The gain of amplifier 605 may be controlled by a digitallycontrollable variable resistor R_(v1), which is connected in seriesbetween the second input and the output of the op-amp 610. In thedescribed embodiment, R_(g) has half the resistance of R_(h). R_(h) isequal to a nominal or intermediate value within the range of resistancesthat can be produced by variable resistor R_(v1). The resistive value ofresistor R_(v1) is controlled by value 615, which is received fromcounter 630. The bandwidth of op-amp 610 can be further limited byadditional capacitance to reduce noise, thereby eliminating the need fora low-pass filter.

[0091] Both variable resistor R_(v1) and variable gain amplifier 605 canbe implemented in a variety of different ways. In certainimplementation(s), variable resistor R_(v1) can be implemented as aseries of binary-weighted resistances, each of which is potentiallyshorted by a corresponding control transistor. The gates of the controltransistors can be connected to the individual bit lines of the value615, so that a logical true on any particular bit line causes acorresponding resistance to be included in the series, and a logicalfalse causes the corresponding resistance to be omitted from the series.

[0092] Optionally, the up/down counter 630 has an enable/disable input625 that enables and disables the counter 630. For example, the counter630 may increment or decrement output value 615 when the enable/disableinput is logically true, but hold output value 615 constant whenever theenable/disable input is logically false.

[0093] The enable/disable input 625 allows the gain of amplifier 605 tobe set during an initialization period. For example, the enable/disableinput 625 may be controlled so that the counter 630 is responsive tofeedback signal F* only during the initialization period. During anoperational period following the initialization period, theenable/disable input 625 may be set to the disable mode so that digitalvalue 615 remains constant. Thus, the gain of amplifier 605 may be setduring an initialization period and may remain constant during asubsequent operational period.

[0094] Utilizing an initialization period to establish a desiredamplifier gain may be advantageous because the surrounding circuits canbe disabled or otherwise configured to generate less noise andinterference, thereby producing a more accurate, steady-state evaluationof the proper gain for the amplifier 605. Once the proper gain isdetermined, it can be held steady, which is desirable during actualoperation of the integrated circuit. Optionally, the “initialization”can be repeated and/or updated at specified intervals to correct forvoltage drifts and other effects.

[0095]FIG. 7 is a schematic view of another exemplary implementation ofa reference voltage driver 410 such as may be used in the scheme of FIG.4A et seq. FIG. 7 shows an alternative implementation that is similar tothe implementation of FIG. 6. As depicted in FIG. 7, the voltage driver410 includes a storage register 710 that is located between the up/downcounter 630 and the variable gain amplifier 605. In this implementation,control circuit(s) (not shown in FIG. 7) may be used to latch the value615 into the register 710, from the counter 630, after an initializationperiod. The register 710 provides this latched value, designated in FIG.7 by reference numeral 705, to the variable gain amplifier 605 tocontrol the gain of the amplifier 605.

[0096] In this implementation, various control signals, collectivelydesignated by the label “Control” and the reference numeral 715 in FIG.7, are available for use by control circuits within, e.g., an IC 400/500to perform various operations with respect to the storage register 710.Such control signals 715 can include a latch signal that latches thevalue 615 into the register 710. In addition, the control signals 715might include data and control signals allowing the value stored by theregister 710 to be written and read. During a typical initialization orcalibration period, the register 710 may be controlled so that itsoutput 705 duplicates the output 615 of the counter 630. Once a steadystate is reached, the register 710 may be controlled so that itmaintains a constant output 705, regardless of further changes in thecounter value 615.

[0097] An advantage of this configuration is that the output value 705that results from initialization can be read by control circuitry todetermine operating parameters of the IC. For example, the controlcircuitry can determine the adjusted gain of the variable amplifier 605and can potentially use this gain value to infer other deviceparameters. Furthermore, the register 710 can optionally be written toby control circuits in order to force the gain of amplifier 605 to somepredetermined level.

[0098] The read/write capabilities of the register 710 can potentiallybe used for a variety of functions. For example, by setting the value705 to a wide range of values it is possible to determine the upper andlower limits of V_(comp) that result in correct operation of the device.Specifically, V_(comp) can be lowered (by reducing the value 705) whiletesting the circuit at each value, until a value is reached that causesa circuit failure. Subsequently, V_(comp) can be raised (by increasingthe value 705) until a value is reached that causes a circuit failure.The range of operational V_(comp) values indicates the available voltagemargin of the circuit. A related strategy is used in the digitalcalibration approach, as is described further below with reference toFIGS. 10A and 10B, to find a mid-point voltage value between the voltagefailure levels. A corresponding mid-point register value 705 may then bewritten to the storage register 710 for use during operational phases.During the determination of the mid-point register value 705 during thecalibration phase, the current register value 705 of the storageregister 710 is read therefrom when the voltage failure levels arereached. As another example, during an operational period, registervalue(s) can be extracted from a parameters table 320 (e.g., of FIGS.3A, 5, 11A, and 11B) and written to the storage register 710 tocompensate for voltage deviations of incoming signals.

[0099] As yet another example of the read/write capabilities of theregister 710, assume that a reference voltage is received from anexternal source and needs to be somehow translated for use by localcircuits. To accomplish this translation using the circuit of FIG. 7,the external reference voltage is received by the variable gainamplifier 605 as V_(nom). During a calibration procedure, a calibratedvalue 705 is determined that will result in a V_(dis)=V_(cm). Thiscalibrated value may be read from the register 710 and an offset valuemay be added. The resultant summed value may then be programmed backinto the register 710 and used during normal operation of the device, toresult in a V_(dis) that is offset from V_(cm) by a desired margin.

[0100] The desired offset value can be determined at design time andadded to the calibrated value 705 after each calibration procedure.Alternatively, the desired offset value can be determined dynamically,as part of an initialization or calibration procedure. For example, thedesired offset value may be calculated based on knowledge of greaternoise contamination at the high or low voltage extreme of V_(cm).Assuming that the interfering noise is located at the high voltageextreme of V_(cm), then a negative offset value is added to thecalibrated value 705 (to form a new calibrated value 705) that lowersV_(dis) with respect to V_(cm). Consequently, the lowered V_(dis)maintains an equal usable voltage swing on the high and low sidesdespite the greater noise contamination on the high voltage extreme ofV_(cm).

[0101]FIG. 8 is a schematic view of yet another exemplary implementationof a reference voltage driver 410 such as may be used in the scheme ofFIG. 4A et seq. This implementation is similar to the previousimplementations of FIGS. 6 and 7, except that the feedback signal F* isused to control a charge pump 810. The charge pump 810 is a capacitivedevice having a control input 815 that receives the feedback signal F*.However, other types of analog storage devices may be used in place ofthe charge pump 810, such as sample and hold devices. The charge pump810 charges a capacitance when the feedback signal F* is logically true,and it discharges the capacitance when the feedback signal F* islogically false. However, an alternative logic can be used instead. Thecharge pump 810 has an analog control voltage output 805 that reflectsthe voltage of the capacitance.

[0102] In response to the feedback signal F*, the analog control voltageproduced at the output 805 is set to increase when V_(dis)<V_(cm) anddecrease when V_(dis)>V_(cm). The analog control voltage output 805 ofthe charge pump 810 is configured to control the gain of the referencevoltage driver 410. In the implementation of FIG. 8, variable resistorR_(v2) comprises an analog variable resistor whose resistance iscontrolled by the output 805 of the charge pump 810. As an example, thevariable resistor R_(v2) can comprise a weighted PMOS adjustableresistor. The variable resistor R_(v2) may be configured to control thegain of the amplifier 605 in a manner similar to that of the variableresistor R_(v1) of the implementation of FIG. 6.

[0103]FIG. 9A is a schematic view of an exemplary implementation of theanalog calibration component 505 (of FIG. 5). In this implementation,the analog calibration component 505 has an input 505A that accepts areceived signal D_(n), and an output 505B that provides the analogcalibration component output D_(n)*. The analog calibration component505 includes a sampler 915 and a set of switches 910. The switchesenable the received data signal 905 to be routed around the sampler 915during operation and through the sampler 915 duringinitialization/calibration. The sampler 915 may comprise a low-passfilter, an integrator, and so forth. In FIG. 9A, the sampler 915 isillustrated as a low-pass filter with a resistor at the sampler input915A and a capacitor at the sampler output 915B.

[0104] The switches 910A and 910B are used to either place the sampler915 inline with the data signal 905 or to bypass the sampler 915.Specifically, the analog calibration component 505 has an input 505Athat receives the data signal 905 at the analog calibration input 505A.When a first of the switches 910B is closed for an initialization phase,the sampler input 915A receives the data signal 905. The sampler output915B is connected through the second of the switches 910B to the analogcalibration output 505B. A switch 910A is connected to enable thesampler 915 to be bypassed by connecting the analog calibration input505A directly to the analog calibration output 505B. Thus, when the twoswitches 910B are both closed and the switch 910A is open, sampler 915samples the data signal 905 and provides the resulting sampled value asthe analog calibration component output D_(n)* to the second input ofthe signal receiver 405N (e.g., in a calibration phase). When the twoswitches 910B are both open and the switch 910A is closed, on the otherhand, the analog calibration component output D_(n)* is the same as thereceived signal D_(n) (e.g., in an operational phase).

[0105] In the described implementation, the sampler 915 determines thecommon mode voltage of the data signal 905 by measuring the averagevoltage of a fifty percent (50%) duty cycle data signal. This commonmode voltage V_(cm) is output as the analog calibration component outputD_(n)* at the analog calibration output 505B and provided to the secondinput of the signal receiver 405N. The signal receiver 405N compares thedistributed voltage V_(dis) to the common mode voltage V_(cm) andproduces the feedback signal F/F* as a result. The feedback signal F/F*is then used by the reference voltage driver 410 to adjust thecompensated voltage V_(comp), as is described above with reference toFIGS. 4A et seq., especially FIGS. 5, 6, and 7.

[0106] The switches 910 are used to route data signals appropriatelyduring respective operational and initialization phases. During aninitialization phase when voltage compensation is being establishedusing the feedback unit 420, the switch 910A is open and the switches910B are both closed so as to utilize the sampler 915. During anoperational phase when it is desired for received data signals to berouted directly (e.g., by bypassing the sampler 915) to the signalreceiver 405N, at least one of the switches 910B is open and the switch910A is closed. The latter switching arrangement may also be employedwhen there is both an analog calibration component 505 and a digitalcalibration component 510 and when it is desired to perform aninitialization using only the digital calibration component 510. Theswitch 910C may optionally be implemented. If present, then it is usedto pre-charge the sampler 915 so as to reduce a start-up or ramp-up timefor the sampler 915 when an initialization phase is beginning. Thispre-charging is accomplished by closing the switch 910C prior toinitialization (e.g., during operational or other phases) to connect thesampler 915 to a, e.g., external reference voltage V_(ref-ext). Theswitch 910C is open during actual initialization periods.

[0107]FIG. 9B is a flowchart illustrating an exemplary method forproviding a compensated voltage using an analog calibration approach.The flowchart 950 includes actions 955-975. These actions 955-975 may beperformed in an order other than that illustrated and/or fully orpartially (substantially) simultaneously. Actions of the flowchart 950may be performed by a receiving unit that is determining a compensationvalue to be used with a transmitting unit under consideration.Furthermore, the actions 955-975 are described below with reference tothe hardware already described above, especially in FIG. 9A, but theycan be performed by other hardware.

[0108] An action 955 comprises sampling data of a signal that isreceived at the receiving unit to produce an average value of the data.The sampler 915 may perform the sampling of the data of the data signal905 and produce the average thereof at the sampler output 915B. Toensure that the average value of the data is the expected mid point of avoltage swing, the data can be from a fifty percent (50%) duty cyclesignal. Examples of such a fifty percent (50%) duty cycle signal include01010101, 00110011, 00010111, 10101010, 11001100, and 10101001, for anexemplary eight-bit data pattern. Other data patterns and other datapattern lengths may alternatively be employed. To be receiving a datasignal having a fifty percent (50%) duty cycle, a receiving unit canload a transmitting unit with a selected data pattern and then instructthe transmitting unit to return the selected data pattern. In thismanner, the receiving unit knows what the average voltage value isexpected to be.

[0109] An action 960 comprises receiving the average value at a signalreceiver, and an action 965 comprises receiving a distributed voltage atthe signal receiver. The average value is represented by the analogcalibration output D_(n)* (in the calibration mode) and can comprise thecommon mode voltage of the received signal D_(n). The distributedvoltage is represented by V_(dis) and is illustrated being input to thesignal receiver 405N. An action 970 comprises comparing the averagevalue of the data to the distributed voltage at the signal receiver todetermine a result. The signal receiver 405N can compare the distributedvoltage V_(dis) to the analog calibration output D_(n)* to determinewhether the latter is greater or less than the former. The result outputfrom the signal receiver 405N is represented by O_(n), and this outputcomprises the feedback signal F/F* in the analog calibration approach.

[0110] An action 975 comprises changing a compensated voltage responsiveto the result, with a consequence thereof being that there is a changingof the distributed voltage. In the described implementation, thereference voltage driver 410 (of FIGS. 4A et seq.) receives the feedbacksignal F/F* and modifies the output voltage thereof (i.e., thecompensated reference voltage V_(comp)). The distributed referencevoltage V_(dis) is a version of the compensated reference voltageV_(comp), so it is consequently changed as well. An arrow 980 leads fromthe action 975 to the action 955 to indicate that all or some of theactions 955-975 are repeated during initialization periods until thefeedback loop is stabilized. Thus, the actions are normally repeateduntil the distributed voltage V_(dis) is approximately equal to theaverage value of the data as produced by the sampler 915 and as receivedat the signal receiver 405N.

[0111]FIG. 10A is a block diagram view of an exemplary implementation ofthe digital calibration component 510 (of FIG. 5). The digitalcalibration component 510 implicitly determines the common mode voltageof the received signal D_(n) and sets the distributed voltage V_(dis)approximately equal thereto at the signal receiver 405N using thereference voltage driver 410. The digital calibration component 510causes the reference voltage driver 410 to increase the compensatedreference voltage V_(comp) that is output therefrom until an error isdetected in interpreting the received signal D_(n). The digitalcalibration component 510 also causes the reference voltage driver 410to decrease the compensated reference voltage V_(comp) until an error isdetected in interpreting the received signal D_(n). From these twoextreme values of the compensated reference voltage V_(comp), amid-point value of the compensated reference voltage V_(comp) isdetermined. This mid-point value of the compensated reference voltageV_(comp) degrades to a distributed voltage V_(dis) that is approximatelyequal to the common mode voltage of the received signal D_(n).

[0112] The digital calibration component 510 controls the compensatedreference voltage V_(comp) of the reference voltage driver 410 using thefeedback signal F* and the control bus 715. An exemplary implementationof the control bus 715 is at least partially described above withreference to FIG. 7. The digital calibration component 510 receives thefeedback signal F and produces the feedback signal F*. The digitalcalibration component 510 also has interfaces for receiving and/orproviding calibration data and for the control bus 715. Internally, thedigital calibration component 510 includes calibration data 1005, acomparison unit 1010, and control logic 1015.

[0113] As is described above with reference to FIG. 5, the signalreceiver 405N accepts as input the distributed reference voltage V_(dis)and the received signal D_(n), and it produces as output O_(n) thefeedback signal F. The feedback signal F is a digital value thatreflects a digital pattern of the received signal D_(n), as long as thedifference between the common mode voltage of the received signal D_(n)and the distributed voltage V_(dis) is not too great.

[0114] The feedback signal F is supplied to the comparison unit 1010 ofthe digital calibration component 510. The comparison unit 1010 alsoaccepts the calibration data from the calibration data register 1005. Inthe described digital calibration embodiment, the calibration datacomprises an expected value to be received from a transmitting unitbecause the transmitting unit was sent the calibration data and asked toreturn it to the receiving unit as the received signal D_(n). With thereceipt of the feedback signal F and the calibration data from thecalibration data register 1005, the comparison unit 1010 can compare thetwo inputs and determine if they are equal. The comparison unit 1010provides a comparison output 1020 to the control logic 1015 in responseto this determination.

[0115] The control logic 1015 uses the comparison output 1020 todigitally control the reference voltage driver 410 until the common modevoltage of the received signal D_(n) is implicitly determined. Thecontrol logic 1015 is configured to cause the reference voltage driver410 to ramp the compensated reference voltage V_(comp) toward either anextreme low voltage or an extreme high voltage until the extreme lowvoltage and the extreme high voltage are both determined.

[0116] The control logic 1015 includes a high point register 1025A and alow point register 1025B to note the extreme high voltage value and theextreme low voltage value using a register value that corresponds to thestorage register 710 (of FIG. 7). In order to determine the extreme highvoltage value, the control logic 1015 uses the feedback signal F* tocause the reference voltage driver 410 to increase the compensatedreference voltage V_(comp) until a receiving failure is detected by thecomparison unit 1010 and signaled to the control logic 1015 via thecomparison output 1020. A failure eventually results because as thecompensated reference voltage V_(comp) increases, the distributedvoltage V_(dis) increases until it is so far above the common modevoltage of the received signal D_(n) that the data values of thereceived signal D_(n) cannot be correctly interpreted at the signalreceiver 405N. In effect, the voltage swing (and related timing margin)becomes sufficiently small for proper signal reception and data valueinterpretation. (The graphs 350 of FIG. 3A provide furtherclarification.)

[0117] After the control logic 1015 has caused the reference voltagedriver 410 to increase the compensated reference voltage V_(comp) untila failure is detected by the comparison unit 1010 and signaled on thecomparison output 1020, the control logic 1015 notes the high extremevoltage value. The control logic 1015 communicates with the referencevoltage driver 410 over the control bus 715 to extract the registervalue stored within the storage register 710. This register value isthen stored at the high point register 1025A to reflect the high extremevoltage value. The control logic 1015 also uses the feedback signal F*to cause the reference voltage driver 410 to decrease the compensatedreference voltage V_(comp) until a receiving failure is detected by thecomparison unit 1010 and signaled to the control logic 1015 via thecomparison output 1020. When the voltage failure point is determined onthe low side, the control logic 1015 again extracts the register valuestored within the storage register 710 via the control bus 715, and itstores this register value at the low point register 1025B to reflectthe low extreme voltage value.

[0118] After high and low point register values have been stored in thehigh point register 1025A and the low point register 1025B,respectively, the control logic 1015 determines a mid point valuetherebetween that corresponds to a mid point voltage value. The midpoint (register) value is then applied to the storage register 710 viathe control bus 715 by the control logic 1015. When the referencevoltage driver 410 sets/modifies the compensated reference voltageV_(comp) according to the mid point register value stored in the storageregister 710 as the current (voltage) compensation value, thedistributed voltage V_(dis) becomes approximately equal to the commonmode voltage of the received signal D_(n). Setting the distributedvoltage V_(dis) approximately equal to the common mode voltage of thereceived signal D_(n) provides for an improved voltage swing forproperly detecting digital values of the received signal D_(n).

[0119] There are many alternatives regarding the content and use of thecalibration data. For example, although the calibration data isillustrated as being received at and sent from the digital calibrationcomponent 510 (via the calibration data register 1005), the transfer ofthe calibration data may be unidirectional in certain implementation(s).More specifically, if the digital calibration component 510 isdetermining the content of the calibration data, then the calibrationdata may be sent from the digital calibration component 510 fortransmission to a transmitting unit (e.g., a memory storage module 315)and subsequent reception therefrom. On the other hand, if a differentcomponent is determining the calibration data instead of the digitalcalibration component 510, then the calibration data may be received atthe digital calibration component 510 and stored at the calibration dataregister 1005 until needed by the comparison unit 1010. The calibrationdata is provided to the comparison unit 1010 to determine whether or notthe expected data value is received with the received signal D_(n)regardless of what component selects the content of the calibrationdata.

[0120] The content of the calibration data may be a pre-selected databit pattern of a predetermined bit length, such as eight (8) bits, butother bit lengths may be used instead. The bit pattern may include both“1s” and “0s”. Alternatively, the bit pattern may be a string of all“1s” or all “0s” to simplify the comparison unit 1010 because only asingle comparator is needed in such an implementation as opposed tomultiple comparators or a single comparator with relatively significantcontrol logic and/or memory buffers to keep track of the comparisonsand/or detected bits across an entire bit pattern. On the other hand, abit pattern with both “1s” and “0s” may enable a more accurate result.In fact, a first bit pattern may be the most problematic bit pattern onthe high voltage side while a second, different bit pattern may be themost problematic bit pattern on the low voltage side. In such a case,both bit patterns may be used for a more accurate result at theirrespective most problematic sides. Furthermore, if the two different bitpatterns are not known a priori, then all possible bit patterns of agiven length of interest (or a subset thereof) may be tried for both thehigh and low voltage sides of the voltage swing so that the mostproblematic bit pattern(s) are eventually used. The data bit pattern ofthe calibration data that is compared at the comparison unit 1010 maytherefore be of different and even changing values and lengths.

[0121] Regardless of the length or content of the data pattern of thecalibration data, the comparison unit 1010 provides a result signal orcomparison output 1020 to the control logic 1015. The comparison output1020 serves to inform the control logic 1015 when there is an error,i.e., when the feedback signal F does not match the calibration data ofthe calibration data register 1005. The comparison output 1020 may onlybe active when there is an error. Alternatively, the comparison output1020 may be logically true (e.g., indicating a favorable report on acomparison) until it switches to logically false (e.g., indicating anunfavorable report on a comparison). Again, positive logic, negativelogic, or some combination thereof may be selected and implemented forthe described components. Although not explicitly shown in FIG. 10A, thecontrol logic 1015 may also be able to control the timing or otheraspects of the comparison unit 1010. In effect, the comparison unit 1010informs the control logic 1015 when there has been a failure with thereceiving and/or interpretation of a received signal D_(n).

[0122] Instead of being separate, the control logic 1015 may be relatedto, part of, or located in/with any control logic of the referencevoltage driver 410, or vice versa. However, to the extent they areseparate, the control bus 715 may be used for the communication of dataand/or instructions between them. The instructions may include theloading and unloading of data register values, including data registervalues 705 for the storage register 710 (of FIG. 7), as is describedabove. The data communicated across the control bus 715 may include(voltage) compensation values that are entered into the storage register710 to set the gain of the reference voltage driver 410. Thecompensation values communicated across the control bus 715 to thestorage register 710 may include data register values 705 selected bythe control logic 1015 for calibration analysis. In other words, thefeedback signal F* may be omitted, and the control logic 1015 maydirectly set the data register values 705 of the storage register 710during a calibration instead of causing the incrementing or decrementingthereof using the feedback signal F*. In this case, the communicationacross the control bus 715 serves as a feedback signal controlling thereference voltage driver 410. The compensation values communicatedacross the control bus 715 to the control logic 1015 may include thevalues to be stored in the registers 1025, including the high pointregister 1025A and the low point register 1025B. Although it is notspecifically shown, the determined digital value representing the midpoint between the high and low voltage failure points may also be storedin a register at the control logic 1015.

[0123]FIG. 10B is a flowchart illustrating an exemplary method forproviding a compensated voltage using a digital calibration approach.The flowchart 1030 includes actions 1035-1075. These actions 1035-1075may be performed in an order other than that illustrated and/or fully orpartially (substantially) simultaneously. Actions of the flowchart 1030may be performed by a receiving unit that is determining a compensationvalue to be used with a transmitting unit under consideration.Furthermore, the actions 1035-1075 are described below with reference tothe hardware already described above, especially that of FIG. 10A, butthey can be performed by other hardware.

[0124] An action 1035 comprises receiving data at a signal receiver. Forexample, the data may be a data pattern that is carried by a receivedsignal D_(n), and the signal receiver may be the signal receiver 405N.An action 1040 comprises receiving a distributed voltage at the signalreceiver. The distributed voltage may be the distributed voltageV_(dis). An action 1045 comprises comparing the data to the distributedvoltage at the signal receiver to determine a result. During aninitialization period, for instance, the signal receiver 405N producesan output O_(n) that is routed to the digital calibration component 510as the feedback signal F (e.g., a result).

[0125] The result from the action 1045 is then compared to an expectedvalue thereof. In the implementation of FIG. 10A, the expected value maybe the calibration data that is stored in the calibration data register1005 and that was previously sent (or otherwise provided) to thetransmitting unit under consideration. An action 1050 comprisesdetermining whether there is a difference between the result and theexpected value. The comparison unit 1010 can compare the expected valueto the feedback signal F to determine whether or not they differ fromone another. If not, then an action 1055 comprises altering a currentvalue of a register that controls a voltage. Thus, the control logic1015 may be configured to respond to the comparison output 1020 bychanging (e.g., increasing or decreasing by one or more units) thedigital register value that is located in the storage register 710 ofthe reference voltage driver 410 via the control bus 715.

[0126] The single asterisk (*) present in the block of the action 1055indicates that the voltage (e.g., a compensated voltage) is changed byaltering the current value of the register. Also, the distributedvoltage (i.e., a derivative of and a version of the compensated voltage)is consequentially changed as well. The block 1075, which also includesa single asterisk (*), may therefore be performed as a result of theaction 1055. Additionally, the double asterisk (**) of the block 1055indicates that control logic or similar may be keeping track of whichdirection (either higher or lower) the current value of the register isto be altered. The altering of the digital register value of the storageregister 710 changes/sets the compensated reference voltage V_(comp),and therefore the distributed reference voltage V_(dis).

[0127] If, on the other hand, there is a difference between the resultand the expected value (from the action 1050), then an action 1060comprises noting (e.g., recording) the current value of the register asan extreme value. The extreme value may be either an extreme high valueor an extreme low value. Hence, the control logic 1015, which can beaware of and/or controlling the direction in which the voltage valuesare changing, is capable of storing the current digital register valueof the storage register 710 (via the control bus 715) into the highpoint register 1025A or the low point register 1025B, respectively.After noting the current register value as an extreme value, an action1065 comprises determining whether or not both the high extreme valueand the low extreme value have been noted. If not, then the action 1055comprises altering the current value of the register. The doubleasterisk (**) of the block 1055 in this context indicates that controllogic or similar may start moving the register value in the oppositedirection, or alternatively, the register value may first be set to adefault or other starting point value prior to the repetitive alteringthereof in the opposite direction.

[0128] If, on the other hand, both the extreme high value and theextreme low value have been noted (as determined from the action 1065),then an action 1070 comprises determining a register value thatcorresponds to the common mode voltage responsive to the noted high andlow extreme values. The common mode voltage may be established at thevoltage reference input of the signal receiver 405N by finding themedian value between the high extreme and the low extreme values asstored in the high and low point registers 1025A and 1025B,respectively. Alternatively, a different (compensation) value may bedetermined by the digital calibration component 510. For example, anoffset may be applied to the median value to achieve the differentcompensation value. Such an offset may be useful if, for example, it isknown that there is greater noise near the high point of the voltageswing. In this situation, the offset may be used to lower thecompensation value below the median value to account for this greaternoise on the high voltage side. After the action 1070, the registervalue is set to the median value or another compensation valuedetermined responsive to the high and low extreme values. The controllogic 1015 may load the storage register 710 of the reference voltagedriver 410 with the median or other voltage compensation value. Anaction 1075 comprises changing a compensated voltage responsive to thecurrent register value setting, with a consequence thereof being thatthere is a changing of the distributed voltage. The distributed voltageV_(dis) at the signal receiver 405N is therefore at least approximatelyequal to the common mode voltage of the data signal D_(n) at the signalreceiver 405N.

[0129] The single asterisk (*) in the block 1075 correlates with thesingle asterisk in the block 1055 and indicates that the action 1075 isalso performed, with likely a different current value of the register,after the action 1055. It should be noted, however, that the action 1055usually alters the current value of the register by incrementing ordecrementing, instead of setting the current value as is performed as aresult of the action 1070 and for the action 1075. Nevertheless, thecontrol logic 1015 may also set the current value of the register in anaction 1055, especially when switching between searching for one extremevalue to searching for the other extreme value, where it may bebeneficial to start both searches at some default value near a projectedcenter.

[0130]FIG. 11A is a block diagram view of an exemplary parameters tableapproach for accommodating signaling. The reference voltage driver 410of FIG. 11A may operate similarly to the reference voltage driver 410 ofFIG. 7, which is described above. However, in the implementation of FIG11A, the reference voltage driver 410 includes a parameters table 320.As such, the reference voltage driver 410 may be especially beneficialin any component that is to receive data signals from more than onetransmitting unit (such as a memory controller module 310 (of FIG. 3A)or another master-type component). In addition to the parameters table320, a control block 1105 and a parameters table bus 1110 have also beenadded to the reference voltage driver 410 of FIG. 11A for interactingwith the parameters table 320.

[0131] As is described above with reference to FIG. 3A, the parameterstable 320 includes multiple entries, with each entry including an ID andassociated attribute(s) for each transmitting unit from which datasignals are to be received. In the implementation of FIG. 11A, theassociated attributes include at least a (voltage) compensation valuefor use in the storage register 710. Utilizing the compensation valueassociated with the ID of a particular transmitting unit, when receivingsignals from that particular transmitting unit, facilitates correctinterpretation of received data.

[0132] When a signal is to be received or is being received from aparticular transmitting unit having a particular ID, the entry in theparameters table 320 that includes that particular ID is accessed andthe compensation value is extracted therefrom. In the implementation ofFIG. 11A, the control block 1105 is configured to extract, e.g., acompensation value from the parameters table 320 using the parameterstable bus 1110 and to load it into the register 710 using the controlbus 715. The reference voltage driver 410 may then establish thecompensated voltage V_(comp) according to the compensation value storedtherein by the control block 1105.

[0133] When a compensation value has been determined, using an analog ora digital calibration approach, for a particular transmitting unithaving a particular ID, the control block 1105 is configured to acquirethe determined compensation value and to store it over the parameterstable bus 1110 into an entry of the parameters table 320 that isassociated with that particular ID. The control block 1105 acquires thedetermined compensation value over the control bus 715 from the storageregister 710 or from another source, such as directly from the digitalcalibration component 510 (of FIG. 10A). The control block 1105 mayoptionally be in communication with or combined with the control logic1015 (of FIG. 10A), or vice versa, in digital calibration approaches. Itshould be noted that although the parameters table bus 1110 isillustrated as being bidirectional, it may instead be unidirectional,especially if there is a second bus in communication with the parameterstable 320 that is operating in a different direction.

[0134]FIG. 11B illustrates an exemplary parameters table 320. Theparameters table 320 may be formed from any general data structure andstored in a memory of a receiving unit. In the implementation of FIG.11B, the parameters table 320 includes a heading row 1115 and multipleentries 1120, specifically 1120(1), 1120(2), through 1120(n). Each entryof the multiple entries 1120 includes an “ID#” and associatedattribute(s). With respect to the “ID#”, as is described above withreference to FIGS. 3A and 5, each transmitting unit or potentialtransmitting unit is associated with an ID to enable or otherwisefacilitate the receiving of signals therefrom (or the transmitting ofsignals thereto). With respect to the associated attributes, theyinclude specifications (from design, operational testing, etc.) for eachparticular transmitting unit such as voltage swing, reference voltagelevel, timing margin, and so forth. It should be noted that although aheading row 1115 is illustrated for clarity in the parameters table 320of FIG. 11B, one need not be present in actual data structureimplementation(s).

[0135] In the parameters table 320 of FIG. 11B, the associatedattributes are represented by a “V_(COMP) Register Value” item and an“Attributes Type” item. The “V_(COMP) Register Value” item may beconsidered an example of an “Attributes Type”, but it is separatedidentified and labeled so as to enable a more-explicit descriptionthereof with reference to FIG. 11A. For example, compensation valuesstored under the “V_(comp) Register Value” item of the heading row 1115comprise digital values that are usable in the storage register 710 forsetting the gain of the variable gain amplifier 605. Thus, when areceiving unit that is incorporating a reference voltage driver 410 ofFIG. 11A is to be receiving signals from a transmitting unit associatedwith the ID#2, for example, the control block 1105 extracts the“V_(COMP) Register Value #2” from the parameters table 320 entry that isassociated with the “ID#2” via the parameters table bus 1110. Thecontrol block 1105 also inserts the “V_(COMP) Register Value #2” intothe storage register 710 via the control bus 715. The compensatedvoltage V_(comp) output from the reference voltage driver 410, and thusthe distributed voltage V_(dis) (which is a degraded version thereof),is appropriately compensated with respect to the transmitting unithaving the “ID#2”, which is the transmitting unit from which signalingis to be received.

[0136] As indicated by the “Attributes Type” item in the heading row1115 of the parameters table 320, there may be other attributesassociated with each “ID#” besides or instead of a “V_(COMP) RegisterValue”. These other attributes may include other values as determined inactual operation, as specified during design, and so forth. For example,the associated attributes for two identification numbers (ID#s) mayindicate that a first one has a voltage swing of 400 mV and a second onehas a voltage swing of 800 mV. These attributes may likewise beextracted from the parameters table 320 (e.g., by the control block 1105via the parameters table bus 1110) and loaded into registers or othercontrol components/settings so that the receiving unit may communicatewith a targeted transmitting unit using appropriate parameters. Althoughthe parameters table 320 is illustrated as being within the referencevoltage driver 410, it may alternatively be partially or entirelylocated somewhere else within the receiving unit, especially when theparameters table 320 stores associated attributes for use by componentsother than the reference voltage driver 410.

[0137] The associated attributes are indicated in the parameters table320 of FIG. 11B according to type (e.g., Types A, K, C, M, . . . x). Insuch an implementation, all or many of the relevant attributes that areidentical for multiple transmitting units may be “extracted” byreferring to a listing of the parameters for a specific type. Such alisting may be stored elsewhere in the parameters table 320 (notexplicitly shown) or elsewhere in the receiving unit. In thisimplementation, the actual elements in the entries 1120 for thedifferent “Type x Attributes” (under the “Attributes Type” item in theheading row 1115) comprise different pointers to different collectionsof attributes for particular transmitting unit types. This approach maybe beneficial from a memory usage perspective when there are, forexample, four transmitting units of Type A and six transmitting units ofType K, and each type has many different relevant parameters to be usedwhen interfacing with a transmitting unit of one of those types.Alternatively, instead of this pointer approach, each entry 1120 in theparameters table 320 may simply list all of the relevant parameters foreach attribute associated with a given ID#.

[0138]FIG. 11C is a flowchart illustrating an exemplary method foraccommodating signaling using a parameters table approach. The flowchart1130, which includes actions 1135-1185, may thus be performed by areceiving unit having a parameters table 320, especially one having atleast one (analog or digital) calibration component. These actions1135-1185 may be performed in an order other than that illustratedand/or fully or partially (substantially) simultaneously. In theflowchart 1130, the actions 1135-1185 are roughly divided into twophases: initialization and operation.

[0139] The actions 1135-1155 correspond to an initialization phase, andthe actions 1165-1185 correspond to an operational phase. The actions1135-1185 of both phases are described below with reference to thehardware already described above, especially that of FIGS. 3A, 11A, and11B, but they can be performed by other hardware. Additionally, thehardware described above with reference to FIGS. 4A, 5, 9A, and 10A maybe used to perform at least part of some of the actions 1135-1185.During an initialization phase, for example, an analog calibrationcomponent 505 or a digital calibration component 510, along with asignal receiver 405N, may be used to determine a (voltage) compensationvalue. During an operational phase, a reference voltage driver 410,along with a parameters table 320, may be employed to utilize thedetermined compensation value while receiving signaling from atransmitting unit.

[0140] During an initialization phase, an action 1135 comprises sendinga data pattern (from the receiving unit) for calibration purposes to anexternal point #1.The data pattern, examples of which are provided abovewith reference to FIGS. 9A and 10A, may be sent from a memory controllermodule 310 to a memory storage module 315A (of FIG. 3A) in the form of awrite data command. An action 1140 comprises instructing the externalpoint #1 to transmit the data pattern back (to the receiving unit).Hence, the memory controller module 310 may instruct the memory storagemodule 315A to return the data pattern using a read data command. Thememory storage module 315A then provides the data pattern to the memorycontroller module 310.

[0141] An action 1145 comprises determining a common mode voltage ofdata signal(s) received from the external point #1 using the datapattern received therefrom. The common mode voltage of data signal(s)received from the external point #1 may be analyzed using an analogcalibration approach (e.g., of FIGS. 9A and 9B) or using a digitalcalibration approach (e.g., of FIGS. 10A and 10B). In an analogcalibration approach, the common mode voltage of the data signals isdetermined “explicitly” using a sampler. For example, the common modevoltage of the received signal D_(n) may be determined by the sampler915 of the analog calibration component 505. In a digital calibrationapproach, on the other hand, the common mode voltage may be determinedmore “implicitly” using a comparison unit, control logic, etc. todetermine a median value that adjusts a supplied voltage to the commonmode voltage at a signal receiver. For example, the common mode voltageof the received signal D_(n) may be determined “implicitly” by settingthe distributed voltage V_(dis) equal thereto at the signal receiver405N using the elements of the digital calibration component 510 tointerpolate the middle of a voltage swing of the received signal D_(n).

[0142] Using a result from, and/or the process of, determining thecommon mode voltage, an action 1150 comprises storing a calibrationvalue in association with the external point #1 in a data structure ofthe receiving unit. For example, a calibration value may be stored inthe parameters table 320 of the memory controller module 310 at an entry1120 that is associated with the ID 325 of the memory storage module315A. One example of an attribute that is storable in the parameterstable 320 is a calibration value, which is a value determined once asystem is interconnected. One example of a calibration value is acompensation value, which is a value that compensates for changes orother deviations of parameter levels. And one example of a compensationvalue is a voltage compensation value, which is the value in the storageregister 710 after an analog or a digital calibration has beencompleted. Hence, the action 1150 may entail the control block 1105retrieving the determined voltage compensation value from the storageregister 710 via the control bus 715 and providing it to the parameterstable 320 via the parameters table bus 1110. Alternatively, for adigital calibration approach, the action 1150 may entail the controllogic 1015 (of FIG. 10A) transferring the voltage compensation value tothe parameters table 320 without it being first stored in the storageregister 710; the control block 1105 and/or the parameters table bus1110 may optionally be involved in this transfer.

[0143] A receiving unit that is implementing the flowchart 1130 has theability to receive signaling from multiple transmitting units. Forexample, the memory controller module 310 may receive signaling fromboth the memory storage module 315A and the memory storage module 315B.Thus, an action 1155 comprises repeating the calibration for relevantmultiple external points. In the memory system 225 implementation ofFIG. 3A, for example, the memory controller module 310 may repeat thecalibration for each memory storage module 315 that it controls. Thisrepetition for all actual or potential transmitting units (e.g., forexternal points #1 through #n) is indicated by the dashed arrow 1160A.Once a calibration value has been stored for all relevant transmittingunits, the initialization phase is completed, and an operational phasebegins. The operational phase becomes active when it is time to receivesignaling from one or more transmitting units.

[0144] After entering the operational phase where signaling needs to bereceived from one or more of multiple transmitting units, an action 1165comprises determining a need to request data from the external point #1.For example, the memory controller module 310 may receive a request fromthe processor 210 for a segment of memory. The memory controller module310 determines which (one or ones) of the memory storage modules 315need to be accessed to retrieve the requested memory segment. An action1170 comprises ascertaining a calibration value that is associated withthe external point #1. The memory controller module 310 ascertains theID 325 of the memory storage module 315 that stores the requested memorysegment, and the memory controller module 310 accesses the entry 1120 inthe parameters table 320 that is associated with that ID 325 in order toascertain the voltage compensation value (e.g., the “V_(comp) RegisterValue”) stored therewith.

[0145] An action 1175 comprises selecting/extracting and/or activatingthe calibration value that is associated with the external point #1. Theassociated calibration value (e.g., a voltage compensation value) may beextracted from the parameters table 320 of the memory controller module310 and loaded into the storage register 710 by the control block 1105using the buses 715 and 1110, for example. Alternatively, the associatedcalibration value may be selected via a pointer mechanism (e.g., a “TypeC Attributes” pointer) from a register of calibration values (e.g., alisting of attributes from the “Type A Attributes” to the “Type XAttributes”). An action 1180 comprises instructing the external point #1to transmit the needed data, and an action 1185 comprises receiving theneeded data from the external point #1 using the calibration value.Hence, the memory controller module 310 may instruct the memory storagemodule 315 to transmit the requested memory segment over the bus 305,and the memory controller module 310 may receive the memory segmentwhile a voltage reference driver 410 is setting a compensated voltageV_(comp) responsive to the voltage compensation value located in thestorage register 710.

[0146] The calibration value (such as a voltage-level-adjusting voltagecompensation value) of the action 1185 may be used to set, adjust, etc.a voltage level, a voltage swing, a timing frequency, a timing margin,and so forth. It should be understood that the calibration value of theoperational phase of the flowchart 1130 (actions 1165-1185) is exemplaryonly and may instead be any general associated attribute of thetransmitting units. The actions 1165-1185 may be repeated for any of thetransmitting units from which data is requested (or otherwise received)during the operational phase, as indicated by the arrow 1190.

[0147] It should be noted that the initialization phase (actions1135-1155) may be entered (and partially or fully completed) at timesother than at start-up. As indicated by the dashed arrow 1160B, theoperational phase may be interrupted for re-calibration. For example,after a predetermined period of time or after a predetermined number ofdetected (e.g., bit or byte) errors, the receiving unit can re-enter theinitialization phase to re-calibrate the calibration values for one ormore of the transmitting units. This re-calibration may account forchanges due to temperature, random drift, usage events, and so forth.

[0148] If delays due to initialization need to be avoided (e.g, in amemory system implementation), re-entering initialization may bepreventable or user configurable. Alternatively, the re-initializationmay be performed gradually, with each interruption of the operationalphase only permitting the re-calibration of a single transmitting unit.Partial re-calibration of a single transmitting unit may also beutilized for implementations where data accuracy and avoiding delays areboth highly critical. Such a partial re-calibration may be effectuatedby storing one or more digital values (e.g., for the storage register710, for an extreme point, etc.) that is reached during there-calibration process and prior to complete re-calibration, and thenrestarting the re-calibration at that or those digital values when theoperational phase can next be interrupted. As yet another alternativefor highly data and time critical implementations, calibration may occurconstantly using a dedicated signal receiver and a dedicated connectionbetween that transmitting unit and the signal receiver of the receivingunit as is described above.

[0149] Although implementations are primarily described herein as beingused to adjust a distributed reference voltage V_(dis) to beapproximately equal to a common mode voltage V_(cm) of a data signal,the described schemes and techniques can also be used to provide adistributed reference voltage V_(dis) having some non-equal relationshipwith the common mode voltage V_(cm). As one example that is describedabove with reference to the implementation of FIG. 7: in the storageregister 710, the value 705 can be changed in a predefined or otherwisedeterminable manner after initialization/calibration to offset ortranslate V_(dis) relative to V_(cm) (e.g., because signal interferenceis particularly problematic at one voltage extreme or the other).Therefore, the distributed reference voltage V_(dis) can be loweredbelow the common mode voltage V_(cm) if noise or another deleteriouseffect is more problematic near the high voltage extreme, or vice versa.

[0150] The various implementations described above provide an effectiveway of establishing a voltage and of compensating or adjusting such avoltage for data signal degradations that occur due to factors such asinterconnect resistances, device leakage currents, noise interference,high frequency timing, deleterious channel effects, and so forth.Although the implementations described herein operate with respect to areference voltage, the same or similar schemes and techniques can beused with respect to other types of DC voltages. For example, thedescribed schemes and techniques can be used to compensate or adjustsupply voltages, ground voltages, bias voltages, and so forth.

[0151] Although details of specific implementations and embodiments aredescribed above, such details are intended to satisfy statutorydisclosure obligations rather than to limit the scope of the followingclaims. Thus, the invention as defined by the claims is not limited tothe specific features described above. Rather, the invention is claimedin any of its forms or modifications that fall within the proper scopeof the appended claims, appropriately interpreted in accordance with thedoctrine of equivalents.

1. A receiving unit that receives one or more data signals, the one ormore data signals having common mode voltages at the receiving unit, thereceiving unit comprising: a voltage driver that supplies a compensatedvoltage in response to a feedback signal, the compensated voltage beingdistributed to produce a distributed voltage relative to which at leastone of the one or more data signals is evaluated; and a feedback unitthat is responsive to the distributed voltage and to a calibrationsignal of the one or more data signals to produce the feedback signal;wherein the feedback unit controls the feedback signal to establish thedistributed voltage at a value that is approximately equal to the commonmode voltage of the calibration signal of the one or more data signals.2. The receiving unit as recited in claim 1, wherein the at least one ofthe one or more data signals is the common mode voltage of thecalibration signal of the one or more data signals.
 3. The receivingunit as recited in claim 1, wherein the at least one of the one or moredata signals is the same data signal as the calibration signal of theone or more data signals.
 4. The receiving unit as recited in claim 1,wherein the feedback unit is active and is receiving the calibrationsignal of the one or more data signals during a calibration phase of thereceiving unit.
 5. The receiving unit as recited in claim 1, wherein thefeedback unit is inactive and is not receiving the calibration signal ofthe one or more data signals during an operational phase of thereceiving unit.
 6. The receiving unit as recited in claim 1, wherein thefeedback unit is active and is receiving the calibration signal of theone or more data signals during an operational phase of the receivingunit via a dedicated signal receiver and a dedicated bus line.
 7. Thereceiving unit as recited in claim 1, further comprising: a plurality ofsignal receivers; wherein the feedback unit includes at least one signalreceiver of the plurality of signal receivers, the at least one signalreceiver receiving as input the distributed voltage.
 8. The receivingunit as recited in claim 1, wherein the receiving unit comprises anintegrated circuit.
 9. The receiving unit as recited in claim 1, whereinthe receiving unit comprises at least one of a memory system, a printedcircuit board, and a computer system.
 10. A receiving unit, comprising:a voltage driver that supplies a compensated voltage, the voltage drivermodifying the compensated voltage based on a feedback signal; and afeedback unit that produces the feedback signal, the feedback unitproducing the feedback signal responsive to a comparison involving anexpected data value, the feedback unit receiving as input a distributedvoltage and a data signal; wherein a change to the compensated voltageresults in a change in the distributed voltage.
 11. The receiving unitas recited in claim 10, further comprising: a data structure having aplurality of entries, each entry of the plurality of entries storing anidentification and an associated attribute for a transmitting unitcorresponding to the identification.
 12. The receiving unit as recitedin claim 11, wherein the associated attribute comprises a voltagecompensation value; and wherein the voltage driver is configured toutilize the voltage compensation value when receiving a data signal fromthe transmitting unit that corresponds to the identification.
 13. Thereceiving unit as recited in claim 12, wherein the voltage driver isfurther configured to utilize the voltage compensation value whenmodifying the compensated voltage based on the feedback signal.
 14. Thereceiving unit as recited in claim 10, wherein the feedback unitincludes at least one signal receiver and at least one calibrationcomponent.
 15. The receiving unit as recited in claim 14, wherein the atleast one calibration component comprises an analog calibrationcomponent, the analog calibration component configured to receive thedata signal and determine a common mode voltage of the data signal; andwherein the at least one signal receiver receives as input thedistributed voltage and the common mode voltage of the data signal andproduces the feedback signal based on a comparison of the distributedvoltage to the common mode voltage of the data signal.
 16. The receivingunit as recited in claim 14, wherein the at least one calibrationcomponent comprises an analog calibration component, the analogcalibration component configured to receive the data signal anddetermine a common mode voltage of the data signal; wherein the at leastone signal receiver receives as input the distributed voltage and thecommon mode voltage of the data signal and produces as output thefeedback signal, and wherein the feedback signal comprises a binaryvalue indicating which of the distributed voltage and the common modevoltage of the data signal is higher.
 17. The receiving unit as recitedin claim 14, wherein the at least one calibration component comprises ananalog calibration component, the analog calibration componentconfigured to receive the data signal and determine a common modevoltage of the data signal; wherein the at least one signal receiverreceives as input the distributed voltage and the common mode voltage ofthe data signal and produces as output the feedback signal, and whereinthe feedback signal causes the voltage driver to increase thecompensated voltage when the distributed voltage is lower than thecommon mode voltage of the data signal and to decrease the compensatedvoltage when the distributed voltage is higher than the common modevoltage of the data signal.
 18. The receiving unit as recited in claim14, wherein the at least one signal receiver receives as input thedistributed voltage and the data signal and produces an output based ona comparison between the distributed voltage and the data signal; andwherein the at least one calibration component comprises a digitalcalibration component, the digital calibration component configured toreceive the output of the at least one signal receiver and to producethe feedback signal.
 19. The receiving unit as recited in claim 14,wherein the at least one signal receiver receives as input thedistributed voltage and the data signal and produces an output based ona comparison between the distributed voltage and the data signal; andwherein the at least one calibration component comprises a digitalcalibration component, the digital calibration component configured toreceive the output of the at least one signal receiver and to producethe feedback signal responsive to a comparison of the output to theexpected data value.
 20. The receiving unit as recited in claim 14,wherein the at least one signal receiver receives as input thedistributed voltage and the data signal and produces an output based ona comparison between the distributed voltage and the data signal;wherein the at least one calibration component comprises a digitalcalibration component, the digital calibration component configured toreceive the output of the at least one signal receiver and to producethe feedback signal responsive to a comparison of the output to theexpected data value; and wherein the feedback signal is produced so asto cause the voltage driver to increase the compensated voltage until ahigh voltage extreme is determined by detecting a data error as a resultof the comparison of the output to the expected data value.
 21. Thereceiving unit as recited in claim 14, wherein the at least one signalreceiver receives as input the distributed voltage and the data signaland produces an output based on a comparison between the distributedvoltage and the data signal; wherein the at least one calibrationcomponent comprises a digital calibration component, the digitalcalibration component configured to receive the output of the at leastone signal receiver and to produce the feedback signal responsive to acomparison of the output to the expected data value; and wherein thefeedback signal is produced so as to cause the voltage driver todecrease the compensated voltage until a low voltage extreme isdetermined by detecting a data error as a result of the comparison ofthe output to the expected data value.
 22. A system having voltagecompensation, comprising: at least one signal receiver, the at least onesignal receiver having a first input receiving a first voltage and asecond input receiving a second voltage, the second voltagecorresponding to a received data signal; and a voltage driver, thevoltage driver supplying the first voltage to the first input of the atleast one signal receiver, the voltage driver configured to change thefirst voltage supplied to the at least one signal receiver responsive toan output of the at least one signal receiver.
 23. The system as recitedin claim 22, wherein the first voltage supplied to the first input ofthe at least one signal receiver is a degraded version of an outputvoltage of the voltage driver.
 24. The system as recited in claim 22,wherein the first voltage supplied to the first input of the at leastone signal receiver is changed to be approximately equal to a commonmode voltage of the received data signal by the voltage driver.
 25. Thesystem as recited in claim 22, wherein the second voltage comprises atleast one of (i) a data voltage of the received data signal and (ii) acommon mode voltage of the received data signal.
 26. An integratedcircuit, comprising: a voltage driver that supplies a compensatedvoltage, the voltage driver modifying the compensated voltage based on afeedback signal; and a feedback unit that produces the feedback signalusing at least one signal receiver and at least one calibrationcomponent, the feedback unit producing the feedback signal responsive toa comparison involving an expected data value, the feedback unitreceiving as input a distributed voltage and a data signal; wherein amodification to the compensated voltage results in a modification of thedistributed voltage so that the distributed voltage becomesapproximately equal to a common mode voltage of the data signal.
 27. Theintegrated circuit as recited in claim 26, wherein at least a version ofthe data signal arrives at the integrated circuit from an externaltransmitting unit; and wherein the at least one signal receiver receivesas a first input the distributed voltage and as a second input at leastone of the data signal and a derivative of the data signal that iscreated by the at least one calibration component.
 28. An electronicarrangement, comprising: a voltage driver means for supplying acompensated voltage, the voltage driver means adapted to modify thecompensated voltage based on a feedback signal; and a feedback means forproducing the feedback signal, the feedback means producing the feedbacksignal responsive to a comparison involving an expected data value, thefeedback means receiving as input a distributed voltage and a datasignal; wherein a change to the compensated voltage results in a changein the distributed voltage.
 29. The electronic arrangement as recited inclaim 28, wherein the feedback means includes analog calibration meansfor determining a common mode voltage of the data signal; and whereinthe feedback means further includes a signal comparison means thatcompares the distributed voltage to the common mode voltage of the datasignal to produce the feedback signal.
 30. The electronic arrangement asrecited in claim 28, wherein the feedback means includes a signalcomparison means that compares the distributed voltage to the datasignal to produce a comparison output; and wherein the feedback meansfurther includes digital calibration means for comparing the expecteddata value to the comparison output to produce the feedback signal atleast partially responsive thereto.
 31. A memory system, comprising: aplurality of memory storage cells; a voltage driver that supplies acompensated voltage, the voltage driver modifying the compensatedvoltage based on a feedback signal; a plurality of signal receivers, theplurality of signal receivers adapted for receiving a data signalcapable of storage within the plurality of memory storage cells, theplurality of signal receivers receiving at least a version of thecompensated voltage; and a feedback unit that produces the feedbacksignal, the feedback unit including a signal receiver of the pluralityof signal receivers, the feedback unit configured to produce thefeedback signal using the data signal received via the signal receiverand responsive to a comparison involving an expected data value.
 32. Thememory system as recited in claim 31, further comprising: a parameterstable, the parameters table including a plurality of entries, each entryof the plurality of entries capable of storing an identification and anassociated voltage compensation value, each identification correspondingto a potential transmitting unit; wherein the voltage driver isconfigured to utilize the associated voltage compensation value tomodify the compensated voltage when the signal receiver of the feedbackunit is receiving the data signal from the potential transmitting unitthat corresponds to the identification.
 33. The memory system as recitedin claim 32, wherein the memory system comprises a memory controller;and wherein the plurality of memory storage cells comprise a buffer. 34.The memory system as recited in claim 31, further comprising: anidentification; wherein the identification enables a master to accessthe plurality of memory storage cells.
 35. The memory system as recitedin claim 34, wherein the memory system comprises a memory storagemodule; and wherein the plurality of memory storage cells comprise amemory storage array.
 36. The memory system as recited in claim 31,further comprising: a bus, the bus in communication with the pluralityof signal receivers; wherein the bus is capable of propagating the datasignal.
 37. A method for providing a compensated voltage when receivingsignals, comprising: supplying a voltage; receiving a data signal froman external point; producing a feedback signal responsive to the datasignal, the voltage, and an expected data value; and modifying thevoltage being supplied in the action of supplying a voltage based, atleast partly, on the feedback signal.
 38. The method as recited in claim37, further comprising: sending a data value to the external point. 39.The method as recited in claim 38, further comprising: instructing theexternal point to return the data value; wherein the action of receivingoccurs after the actions of sending and instructing, and wherein thedata signal includes the data value.
 40. The method as recited in claim37, wherein the action of producing comprises the actions of:determining a common mode voltage of the data signal, the common modevoltage of the data signal potentially reflective of the expected datavalue; and comparing the common mode voltage of the data signal to aversion of the voltage to produce the feedback signal.
 41. The method asrecited in claim 37, wherein the action of modifying comprises theactions of: increasing the voltage if a common mode voltage of the datasignal is greater than a version of the voltage; and decreasing thevoltage if a common mode voltage of the data signal is less than aversion of the voltage.
 42. The method as recited in claim 37, whereinthe action of producing comprises the actions of: comparing the datasignal to a version of the voltage to produce a preliminary feedbacksignal; comparing the preliminary feedback signal to the expected datavalue to determine whether or not a data receiving error has occurred;and producing the feedback signal responsive to determining whether ornot a data receiving error has occurred.
 43. A method for voltagecompensation, comprising: sampling data at a sampler to produce anaverage value of the data; receiving the average value of the data as afirst input of a signal receiver; receiving a distributed voltage as asecond input of the signal receiver; comparing the average value of thedata to the distributed voltage at the signal receiver to determine anoutput therefrom; and changing the distributed voltage responsive to theoutput.
 44. The method as recited in claim 43, further comprising:transmitting the data to a destination; instructing the destination totransmit the data from the destination so that the data can be sampledin the action of sampling data at a sampler.
 45. The method as recitedin claim 43, wherein the action of sampling data at a sampler comprisesat least one of the following actions: low pass filtering the data at alow pass filter; and integrating the data at an integrator.
 46. Themethod as recited in claim 43, wherein the data comprises a data patternhaving a duty cycle of approximately fifty percent (50%).
 47. The methodas recited in claim 46, wherein the data pattern is selected from thegroup comprising 01010101, 00110011, 00010111, 10101010, 11001100, and10101001.
 48. The method as recited in claim 43, wherein the action ofchanging the distributed voltage responsive to the output comprises:changing a value of an up/down counter responsive to the output;applying the value of the up/down counter to establish a gain of avariable gain voltage amplifier; and amplifying a nominal voltage withthe variable gain voltage amplifier to produce a compensated voltage;wherein a change to the distributed voltage results from the action ofamplifying a nominal voltage with the variable gain voltage amplifier toproduce a compensated voltage.
 49. The method as recited in claim 43,wherein the action of changing the distributed voltage responsive to theoutput comprises: changing a value of an up/down counter responsive tothe output; loading a register with the value of the up/down counter;providing the value from the register to a variable gain voltageamplifier to establish a gain thereof; and amplifying a nominal voltagewith the variable gain voltage amplifier to produce a compensatedvoltage; wherein a change to the distributed voltage results from theaction of amplifying a nominal voltage with the variable gain voltageamplifier to produce a compensated voltage.
 50. A method for voltagecompensation, comprising: sampling data to produce a first voltage;receiving the first voltage at an input component; receiving a secondvoltage at the input component; comparing the first voltage to thesecond voltage to produce a feedback signal; changing a third voltageresponsive to the feedback signal; wherein the second voltage is adegraded version of the third voltage.
 51. The method as recited inclaim 50, wherein the first voltage comprises a common mode voltage ofthe data.
 52. The method as recited in claim 50, wherein the inputcomponent comprises a signal receiver and the action of comparing isperformed at the signal receiver.
 53. An integrated circuit, comprising:a voltage driver that supplies a compensated voltage, the voltage drivermodifying the compensated voltage based on a feedback signal; acalibration component receiving a data signal, the calibration componentincluding a sampler, the sampler adapted to receive the data signal andto produce a common mode voltage of the data signal; and a signalreceiver comparing a first input to a second input and outputting thefeedback signal, the signal receiver receiving a distributed voltage atthe first input and the common mode voltage of the data signal at thesecond input; wherein the distributed voltage comprises a degradedversion of the compensated voltage.
 54. The integrated circuit asrecited in claim 53, wherein the sampler comprises at least one of alow-pass filter and an integrator.
 55. The integrated circuit as recitedin claim 53, wherein the common mode voltage of the data signalcomprises an average value of the data signal.
 56. The integratedcircuit as recited in claim 53, wherein the calibration componentcomprises at least one switch in series with the sampler, the at leastone switch being closed during an initialization phase and open duringan operational phase.
 57. The integrated circuit as recited in claim 53,wherein the calibration component comprises at least one switch inparallel with the sampler, the at least one switch being open during aninitialization phase and closed during an operational phase.
 58. Theintegrated circuit as recited in claim 53, wherein the calibrationcomponent comprises a pre-charging component, the pre-charging componentadapted to pre-charge the sampler prior to an initialization phase. 59.The integrated circuit as recited in claim 53, wherein the voltagedriver has an adjustable gain that changes based on the feedback signalsuch that the compensated voltage is increased when the distributedvoltage is lower than the common mode voltage of the data signal anddecreased when the distributed voltage is greater than the common modevoltage of the data signal.
 60. The integrated circuit as recited inclaim 53, wherein the voltage driver has an adjustable gain that changesas an up/down counter is changed based on the feedback signal; andwherein the adjustable gain changes such that the compensated voltage isincreased when the distributed voltage is lower than the common modevoltage of the data signal and decreased when the distributed voltage isgreater than the common mode voltage of the data signal.
 61. Theintegrated circuit as recited in claim 53, wherein the voltage driverhas an adjustable gain that changes based on the feedback signal suchthat the compensated voltage is increased when the distributed voltageis lower than the common mode voltage of the data signal and decreasedwhen the distributed voltage is greater than the common mode voltage ofthe data signal; and wherein the adjustable gain is determined by adigital value stored in a register.
 62. A system for voltagecompensation, comprising: sampling means for sampling a received datasignal to produce an average value of the received data signal;receiving means for receiving the average value of the received datasignal as a first input and a distributed voltage as a second input;comparing means for comparing the average value of the received datasignal to the distributed voltage to determine a comparison output;voltage means for modifying a compensated voltage responsive to thecomparison output; and degrading means for degrading the compensatedvoltage to the distributed voltage.
 63. A method for voltagecompensation, comprising: receiving data as a first input of a signalreceiver; receiving a distributed voltage as a second input of thesignal receiver; comparing the data to the distributed voltage at thesignal receiver to determine at least one result therefrom; determiningwhether there is a difference between the at least one result and anexpected value; if there is a difference, noting a current value of aregister as an extreme value; and if there is not a difference, alteringthe current value of the register; and changing a compensated voltageresponsive to the current value of the register; wherein a change to thecompensated voltage results in a change in the is distributed voltage.64. The method as recited in claim 63, wherein the at least one resultand the expected value each comprise an eight (8)-bit data pattern. 65.The method as recited in claim 63, wherein the action of noting acurrent value of a register as an extreme value comprises the action ofstoring the current value of the register into at least one of a highvoltage point register and a low voltage point register.
 66. The methodas recited in claim 63, wherein the action of altering the current valueof the register comprises at least one of the following actionsincrementing the current value of the register, decrementing the currentvalue of the register, and setting the current value of the register toa new value.
 67. The method as recited in claim 63, further comprising:determining whether a high extreme value and a low extreme value havebeen noted; if so, determining an intermediate value between the highextreme value and the low extreme value; and setting the current valueof the register to equal the intermediate value.
 68. The method asrecited in claim 67, wherein the action of determining an intermediatevalue between the high extreme value and the low extreme value comprisesat least one of the following actions: determining an intermediate valueusing a median value between the high extreme value and the low extremevalue; and determining an intermediate value using a median valuebetween the high extreme value and the low extreme value and an offsettherefrom.
 69. A receiving unit, comprising: a voltage driver thatsupplies a compensated voltage, the voltage driver modifying thecompensated voltage based on a feedback signal; a signal receivercomparing a first input to a second input and outputting a result, thesignal receiver receiving a distributed voltage at the first input and adata signal at the second input; and a calibration component receivingthe result and producing the feedback signal; the calibration componentincluding a comparison unit and calibration data; the comparison unitconfigured to receive the result and the calibration data, to comparethe result to the calibration data, and to determine whether the resultdiffers from the calibration data; wherein the distributed voltagecomprises a degraded version of the compensated voltage.
 70. Thereceiving unit as recited in claim 69, wherein the feedback signal isformed responsive to the determination by the comparison unit of whetherthe result differs from the calibration data.
 71. The receiving unit asrecited in claim 69, wherein the feedback signal is formed responsive tothe determination by the comparison unit of whether the result differsfrom the calibration data such that the voltage driver modifies thecompensated voltage when the result does not differ from the calibrationdata.
 72. The receiving unit as recited in claim 69, further comprising:control logic, the control logic including a high voltage point registerand a low voltage point register, the control logic configured toprovide the feedback signal such that the voltage driver modifies thecompensated voltage when the result does not differ from the calibrationdata, and wherein the control logic is further configured to store aregister value into at least one of the high voltage point register andthe low voltage point register when the result does differ from thecalibration data.
 73. The receiving unit as recited in claim 69, furthercomprising: control logic, the control logic including a high voltagepoint register and a low voltage point register; the control logicconfigured to provide the feedback signal such that the voltage drivermodifies the compensated voltage when the result does not differ fromthe calibration data; wherein the control logic is further configured tostore a register value into at least one of the high voltage pointregister and the low voltage point register when the result does differfrom the calibration data; and wherein the control logic is adapted todetermine an intermediate voltage point value based on the high voltagepoint register and the low voltage point register and to provide theintermediate voltage point value to the voltage driver.
 74. Thereceiving unit as recited in claim 69, wherein the voltage driverincludes a storage register that controls a gain of the voltage driver;and further comprising: control logic, the control logic including ahigh voltage point register and a low voltage point register; thecontrol logic configured to provide the feedback signal at leastindirectly to the storage register such that the voltage driver modifiesthe compensated voltage when the result does not differ from thecalibration data; wherein the control logic is further configured tostore a register value from the storage register of the voltage driverinto at least one of the high voltage point register and the low voltagepoint register when the result does differ from the calibration data;and wherein the control logic is adapted to determine an intermediatevoltage point value based on the high voltage point register and the lowvoltage point register and to provide the intermediate voltage pointvalue to the storage register of the voltage driver.
 75. A method forcalibrating reception, comprising: sending a first data pattern to afirst external point; instructing the first external point to transmitthe first data pattern back; determining a first common mode voltage ofa first data signal carrying the first data pattern back; determining afirst calibration value based on the action of determining a firstcommon mode voltage of a first data signal; and storing the firstcalibration value in association with a first identification of thefirst external point.
 76. The method as recited in claim 75, wherein theaction of sending a first data pattern to a first external pointcomprises the action of sending the first data pattern to a memorystorage module.
 77. The method as recited in claim 75, wherein themethod is performed by a memory controller.
 78. The method as recited inclaim 75, wherein the action of determining a first calibration valuebased on the action of determining a first common mode voltage of afirst data signal comprises the action of determining the firstcalibration value such that the first calibration value may be utilizedby a voltage driver to adjust a compensated voltage to improve a voltagemargin usable for receiving future data signals from the first externalpoint.
 79. The method as recited in claim 75, further comprising:sending a second data pattern to a second external point; instructingthe second external point to transmit the second data pattern back;determining a second common mode voltage of a second data signalcarrying the second data pattern back; determining a second calibrationvalue based on the action of determining a second common mode voltage ofa second data signal; and storing the second calibration value inassociation with a second identification of the second external point.80. The method as recited in claim 79, wherein the first data pattern isidentical to the second data pattern.
 81. The method as recited in claim79, wherein the first data pattern is different from the second datapattern.
 82. The method as recited in claim 79, further comprising:determining a need to request data from the second external point;ascertaining that the second calibration value is associated with thesecond external point; activating the second calibration value;instructing the second external point to transmit the needed data; andreceiving the needed data from the second external point using thesecond calibration value.
 83. The method as recited in claim 75, whereinthe action of determining a first common mode voltage of a first datasignal carrying the first data pattern back comprises at least one ofthe following actions: determining the first common mode voltage of thefirst data signal using at least a sampler; and determining the firstcommon mode voltage of the first data signal using at least a comparisonunit, control logic, and a feedback signal.
 84. The method as recited inclaim 75, wherein the first calibration value comprises a voltagecompensation value.
 85. The method as recited in claim 75, furthercomprising: activating the first calibration value; instructing thefirst external point to transmit requested data; and receiving therequested data from the first external point using the first calibrationvalue.
 86. A method for voltage compensation, comprising: determining afirst compensation value based, at least partly, on a first signalreceived from a first external point; storing the first compensationvalue in association with a first identification of the first externalpoint; determining a second compensation value based, at least partly,on a second signal received from a second external point; and storingthe second compensation value in association with a secondidentification of the second external point.
 87. The method as recitedin claim 86, wherein: the action of storing the first compensation valuein association with a first identification of the first external pointfurther comprises the action of storing the first compensation value ina parameters data structure; and the action of storing the secondcompensation value in association with a second identification of thesecond external point further comprises the action of storing the secondcompensation value in the parameters data structure.
 88. The method asrecited in claim 86, further comprising: extracting the secondcompensation value; activating the second compensation value; andreceiving data from the second external point using the secondcompensation value to adjust a voltage.
 89. A method for initializingand operating a system having at least receiving functionality,comprising: executing an initialization, the initialization comprising:sending at least one data pattern to a plurality of external points;instructing the plurality of external points to transmit the at leastone data pattern back in a respective plurality of signals; determininga respective plurality of calibration values for the plurality ofexternal points responsive to receipt of the respective plurality ofsignals; and storing the respective plurality of calibration values inassociation with a respective plurality of identifications of theplurality of external points; and implementing an operational phase, theoperational phase comprising: determining that data is to be receivedfrom a particular external point of the plurality of external points;ascertaining a particular calibration value of the plurality ofcalibration values, the particular calibration value associated with theparticular external point; activating the particular calibration value;and receiving the data from the particular external point using theparticular calibration value.
 90. The method as recited in claim 89,wherein the system comprises a memory system.
 91. The method as recitedin claim 89, wherein the system comprises a memory controller, and theplurality of external points comprise a plurality of memory storagemodules.
 92. The method as recited in claim 89, wherein the actions ofthe implementing an operational phase action are repeated for multipleexternal points of the plurality of external points.
 93. The method asrecited in claim 89, wherein the actions of the executing aninitialization action are repeated for at least one external point ofthe plurality of external points.
 94. A method for receiving data,comprising: determining a need to request first data from a firstexternal point; ascertaining that a first calibration value isassociated with the first external point; activating the firstcalibration value; requesting the first external point to transmit thefirst data; and receiving the first data from the first external pointusing the first calibration value.
 95. The method as recited in claim94, further comprising: determining a need to request second data from asecond external point; ascertaining that a second calibration value isassociated with the second external point; activating the secondcalibration value; requesting the second external point to transmit thesecond data; and receiving the second data from the second externalpoint using the second calibration value.
 96. The method as recited inclaim 94, wherein the action of ascertaining that a first calibrationvalue is associated with the first external point comprises the actionof accessing a parameters table at an entry having an identificationthat is associated with the first external point, the entry includingthe first calibration value.
 97. The method as recited in claim 94,wherein the action of activating the first calibration value comprisesthe action of loading a register with the first calibration value. 98.The method as recited in claim 94, wherein the action of receiving thefirst data from the first external point using the first calibrationvalue comprises the action of adjusting a voltage that is used tointerpret received signaling responsive to the first calibration value.99. An integrated circuit configured to perform actions comprising:determining a need to request first data from a first external point;ascertaining that a first calibration value is associated with the firstexternal point from a parameters data structure; activating the firstcalibration value; requesting the first external point to transmit thefirst data; receiving the first data from the first external point usingthe first calibration value; determining a need to request second datafrom a second external point; ascertaining that a second calibrationvalue is associated with the second external point from the parametersdata structure; activating the second calibration value; requesting thesecond external point to transmit the second data; and receiving thesecond data from the second external point using the second calibrationvalue.
 100. An integrated circuit comprising: a voltage driver, thevoltage driver adapted to modify a voltage output therefrom responsiveto a content of a digital register; a parameters data structure, theparameters data structure including a plurality of entries, each entryof the plurality of entries including an identification and anassociated digital value; and control logic in communication with thevoltage driver and the parameters data structure; the control logicconfigured to determine that signaling is to be received from anexternal point, the external point having a particular identification;the control logic further configured to extract a particular associateddigital value that is associated with the particular identification ofthe external point from the parameters data structure; the control logicfurther configured to store the particular associated digital value asthe content of the digital register.
 101. The integrated circuit asrecited in claim 100, wherein the identification comprises at least oneof an address and a location on a bus.
 102. The integrated circuit asrecited in claim 100, wherein the control logic is further configured todetermine associated digital values for the plurality of entries byreceiving signaling from external points and to store the associateddigital values in the parameters data structure.
 103. The integratedcircuit as recited in claim 100, wherein the control logic is furtherconfigured to determine associated digital values for the plurality ofentries by receiving signaling from external points and to store theassociated digital values in the parameters data structure by at leastone of copying and moving the content of the digital register into anentry of the plurality of entries.
 104. A receiving unit, comprising:data structure means for storing a plurality of parameter-relatedentries, each parameter-related entry of the plurality ofparameter-related entries including an identification and at least oneassociated attribute value; determining means for determining a need torequest data from an external point, the external point having aparticular identification; ascertaining means for ascertaining from thedata structure means a particular associated attribute value, theparticular associated attribute value included in a particular entryhaving the particular identification of the external point; activatingthe particular associated attribute value; requesting the external pointto transmit the needed data; and receiving the needed data from theexternal point using the particular associated attribute value.
 105. Anintegrated circuit, comprising: a data structure, the data structureincluding a plurality of entries, each entry of the plurality of entriesincluding an identification and a calibration value, the identificationassociated with an external point from which signaling may be received,the calibration value being previously determined in a calibrationprocedure with the external point and being usable to improve voltagemargin when receiving signaling from the external point.
 106. A memorysystem, comprising: a plurality of memory storage modules, each memorystorage module including a plurality of memory storage cells and anassociated identification; at least one memory controller, the at leastone memory controller including a data structure; the data structureincluding a plurality of entries, each entry of the plurality of entriesincluding an associated identification and an associated compensationvalue; the associated identification of each entry associated with anassociated memory storage module of the plurality of memory storagemodules, the associated compensation value of each entry associated withthe associated memory storage module; the at least one memory controllerconfigured to determine each associated compensation value of each entryby receiving signaling from the associated memory storage module. 107.The memory system as recited in claim 106, wherein the at least onememory controller includes a voltage driver that is adapted to use theassociated compensation value to improve voltage margin when receivingsignaling from the associated memory storage module.